llvm-project

Commit Graph

Author	SHA1	Message	Date
Matt Arsenault	190a17bbd1	AMDGPU: Fix i16 arithmetic pattern redundancy There were 2 problems here. First, these patterns were duplicated to handle the inverted shift operands instead of using the commuted PatFrags. Second, the point of the zext folding patterns don't apply to the non-0ing high subtargets. They should be skipped instead of inserting the extension. The zeroing high code would be emitted when necessary anyway. This was also emitting unnecessary zexts in cases where the high bits were undefined. llvm-svn: 374092	2019-10-08 17:36:38 +00:00
Matt Arsenault	1237aa2996	AMDGPU/GlobalISel: Fix selection of 16-bit shifts llvm-svn: 373945	2019-10-07 19:10:44 +00:00
Matt Arsenault	e5b28b98e9	AMDGPU/GlobalISel: Select G_LSHR llvm-svn: 366256	2019-07-16 20:25:43 +00:00

Author

SHA1

Message

Date

Matt Arsenault

190a17bbd1

AMDGPU: Fix i16 arithmetic pattern redundancy

There were 2 problems here. First, these patterns were duplicated to
handle the inverted shift operands instead of using the commuted
PatFrags.

Second, the point of the zext folding patterns don't apply to the
non-0ing high subtargets. They should be skipped instead of inserting
the extension. The zeroing high code would be emitted when necessary
anyway. This was also emitting unnecessary zexts in cases where the
high bits were undefined.

llvm-svn: 374092

2019-10-08 17:36:38 +00:00

Matt Arsenault

1237aa2996

AMDGPU/GlobalISel: Fix selection of 16-bit shifts

llvm-svn: 373945

2019-10-07 19:10:44 +00:00

Matt Arsenault

e5b28b98e9

AMDGPU/GlobalISel: Select G_LSHR

llvm-svn: 366256

2019-07-16 20:25:43 +00:00

3 Commits