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Commit Graph

Author	SHA1	Message	Date
Kang Zhang	513976df2e	[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118	2020-04-16 16:22:43 +00:00
Roland Froese	732fe22454	[PowerPC] Avoid scalarization of vector truncate The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead. Differential Revision: https://reviews.llvm.org/D56507 llvm-svn: 353724	2019-02-11 17:29:14 +00:00
Roland Froese	42f58498c5	[PowerPC] Add vector truncate test to prep for D56507 NFC llvm-svn: 353344	2019-02-06 21:34:44 +00:00

Author

SHA1

Message

Date

Kang Zhang

513976df2e

[PowerPC] Ignore implicit register operands for MCInst

Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118

2020-04-16 16:22:43 +00:00

Roland Froese

732fe22454

[PowerPC] Avoid scalarization of vector truncate

The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead.

Differential Revision: https://reviews.llvm.org/D56507

llvm-svn: 353724

2019-02-11 17:29:14 +00:00

Roland Froese

42f58498c5

[PowerPC] Add vector truncate test to prep for D56507 NFC

llvm-svn: 353344

2019-02-06 21:34:44 +00:00

3 Commits