4 Commits

Author	SHA1	Message	Date
Amy Kwan	b3147058de	[PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM ... This patch implements the 128-bit vector divide extended builtins in Clang/LLVM. These builtins map to the vdivesq and vdiveuq instructions respectively. Differential Revision: https://reviews.llvm.org/D87729	2020-09-22 11:31:44 -05:00
Albion Fung	05aa997d51	[PowerPC] Implement __int128 vector divide operations ... This patch implements __int128 vector divide operations for ISA3.1. Differential Revision: https://reviews.llvm.org/D85453	2020-09-15 15:19:35 -04:00
Amy Kwan	76b0f99ea8	[PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang ... This patch implements the function prototypes vec_mulh and vec_dive in order to utilize the vector multiply high (vmulh[s|u][w|d]) and vector divide extended (vdive[s|u][w|d]) instructions introduced in Power10. Differential Revision: https://reviews.llvm.org/D82609	2020-08-26 23:14:34 -05:00
Amy Kwan	1dc1a3fb0c	[PowerPC] Implement low-order Vector Multiply, Modulus and Divide Instructions ... This patch aims to implement the low order vector multiply, divide and modulo instructions available on Power10. The patch involves legalizing the ISD nodes MUL, UDIV, SDIV, UREM and SREM for v2i64 and v4i32 vector types in order to utilize the following instructions: - Vector Multiply Low Doubleword: vmulld - Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud - Vector Divide Word/Doubleword: vdivsw, vdivsd, vdivuw, vdivud Differential Revision: https://reviews.llvm.org/D82510	2020-07-23 17:18:36 -05:00