4 Commits

Author	SHA1	Message	Date
Matthias Braun	e40d89ef9b	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 ... Re-apply r241926 with an additional check that r13 and r15 are not used for LDRD/STRD. See http://llvm.org/PR24190. This also already includes the fix from r241951. Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 242742	2015-07-21 00:18:59 +00:00
Matthias Braun	731e359e70	Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2" ... This reverts commit r241926. This caused http://llvm.org/PR24190 llvm-svn: 242735	2015-07-20 23:17:20 +00:00
Matthias Braun	e4ba6b8c24	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 ... Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926	2015-07-10 18:28:49 +00:00
Oliver Stannard	51b1d460cb	[ARM] Enable DP copy, load and store instructions for FPv4-SP ... The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172	2014-08-21 12:50:31 +00:00