Commit Graph

281327 Commits

Author SHA1 Message Date
Gabor Horvath d2c562dd0e Attempt to make the PS4 build bot happy.
llvm-svn: 323590
2018-01-27 16:38:56 +00:00
Gabor Horvath c78d99a84b [ASTImporter] Add support to import some AST nodes:
* CXXOperatorCallExpr
* SizeOfPackExpr
* DependentTemplateSpecializationType
* DependentSizedArray
* CXXTypeidExpr
* Fix importing CXXTemporaryObjectExpr

Some of the changes are based on
https://github.com/haoNoQ/clang/blob/summary-ipa-draft/lib/AST/ASTImporter.cpp

Differential Revision: https://reviews.llvm.org/D42335

llvm-svn: 323589
2018-01-27 16:11:45 +00:00
Amaury Sechet 1ae296da36 Regenerate test results for and-su.ll . NFC
llvm-svn: 323588
2018-01-27 16:00:10 +00:00
Simon Pilgrim 516cee12cc [X86][SSE] Add broadcast from v2i32 memory tests (PR34394)
llvm-svn: 323587
2018-01-27 15:54:57 +00:00
Jan Kratochvil 6492caab1d Remove unused class declarations
Simplification by removing excessive DWARFCompileUnit references for D40466 .

Differential revision: https://reviews.llvm.org/D42613

llvm-svn: 323586
2018-01-27 14:35:33 +00:00
Craig Topper 2c570eaa00 [TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of vXi1 vectors into logic ops.
This transform was already being done for setcc of scalar i1. This extends it to vectors.

llvm-svn: 323585
2018-01-27 09:10:58 +00:00
George Rimar 37304c475a [ELF] - Extend lto/asmundef.ll testcase.
Patch adds one more module with non-prevailing
version of asm symbol, defined in main module

This is for D42107, which is under review. 
Extended version of testcase would fail with the
diff 9 version of patch posted.

llvm-svn: 323584
2018-01-27 09:04:47 +00:00
Craig Topper c80f0ced84 [SelectionDAG] Make DAGTypeLegalizer::PromoteSetCCOperands handle SETEQ/SETNE correctly for vector types.
The code was using getValueSizeInBits and combining with the result of a call to DAG.ComputeNumSignBits. But for vector types getValueSizeInBits returns the width of the full vector while ComputeNumSignBits is going to give a number no larger than the width of a single element. So we should be using getScalarValueSizeInBits to get the element width.

llvm-svn: 323583
2018-01-27 08:41:03 +00:00
Amara Emerson 77a5c96560 [GlobalISel][Legalizer] Convert the FP constants to the right APFloat type for G_FCONSTANT.
We weren't converting the immediate ConstantFP during legalization, which caused
the wrong bit patterns to be emitted for half type FP constants.

Fixes PR36106.

llvm-svn: 323582
2018-01-27 07:07:20 +00:00
Alexey Bataev f86be12182 Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle."
This reverts commit r323530 to fix possible problems in users code.

llvm-svn: 323581
2018-01-27 02:42:21 +00:00
Alexey Bataev dce1614d75 Revert "[SLP] Removed the warning about unused variable, NFC."
This reverts commit r323533 to fix possible problems in users code.

llvm-svn: 323580
2018-01-27 02:42:17 +00:00
Rui Ueyama 57175aa1e9 Add the /order option.
With the /order option, you can give an order file. An order file
contains symbol names, one per line, and the linker places comdat
sections in that given order. The option is used often to optimize
an output binary for (in particular, startup) speed by improving
locality.

Differential Revision: https://reviews.llvm.org/D42598

llvm-svn: 323579
2018-01-27 00:34:46 +00:00
Akira Hatanaka e5dbb64652 [CodeGen] Use the non-virtual alignment when emitting the base
constructor.

Previously, clang would emit an over-aligned (16-byte) store to
initialize B::x in B's base constructor when compiling the following
code:

struct A {
  __attribute__((aligned(16))) double data1;
};

struct B : public virtual A {
  B() : x(123) {}
  double a;
  int x;
};

struct C : public virtual B {};

void test() { B b; C c; }

This was happening because the code in IRGen that does member
initialization was using the alignment of a complete object instead of
the non-virtual alignment.

This commit fixes the bug.

rdar://problem/36382481

Differential Revision: https://reviews.llvm.org/D42521

llvm-svn: 323578
2018-01-27 00:34:09 +00:00
Matt Davis 1edb905e82 Always allow "#pragma region".
Summary:
Both MS and PS4 targets are capable of recognizing the
existence of:  #pragma region, #pragma endregion.

Since this pragma is only a hint for certain editors, and has no logic,
it seems helpful to permit this pragma in all cases, not just MS compatibility mode.



Reviewers: rnk, rsmith, majnemer

Reviewed By: majnemer

Subscribers: Quuxplusone, probinson, majnemer, cfe-commits

Differential Revision: https://reviews.llvm.org/D42248

llvm-svn: 323577
2018-01-27 00:25:29 +00:00
Vedant Kumar cff94627cf [InstrProfiling] Don't exit early when an unused intrinsic is found
This fixes a think-o in r323574.

llvm-svn: 323576
2018-01-27 00:01:04 +00:00
Vedant Kumar 51ce668d12 [LangRef] Update out-of-date instrprof names
llvm-svn: 323575
2018-01-26 23:54:25 +00:00
Vedant Kumar 1ee511c19c [InstrProfiling] Improve compile time when there is no work
When there are no uses of profiling intrinsics in a module, and there's
no coverage data to lower, InstrProfiling has no work to do.

llvm-svn: 323574
2018-01-26 23:54:24 +00:00
Justin Bogner 5db11e3181 update_mir_test_checks: Accept "." in function names
llvm-svn: 323573
2018-01-26 22:56:31 +00:00
Craig Topper 8a444ee67c [X86] Use vpternlog to implement vector not under AVX512.
Previously we had to materialize all 1s in a register using vpternlog or pcmpeq and then xor with that. By using vpternlog directly we can do it in one operation.

This is implemented using isel patterns, but we should maybe consider creating a generalized vpternlog combiner.

llvm-svn: 323572
2018-01-26 22:17:40 +00:00
Sanjay Patel 5bce08ddff [x86] auto-generate complete checks; NFC
llvm-svn: 323571
2018-01-26 22:06:07 +00:00
Vedant Kumar e48597a50e [InstCombine] Preserve debug values for eliminable casts
A cast from A to B is eliminable if its result is casted to C, and if
the pair of casts could just be expressed as a single cast. E.g here,
%c1 is eliminable:

  %c1 = zext i16 %A to i32
  %c2 = sext i32 %c1 to i64

InstCombine optimizes away eliminable casts. This patch teaches it to
insert a dbg.value intrinsic pointing to the final result, so that local
variables pointing to the eliminable result are preserved.

Differential Revision: https://reviews.llvm.org/D42566

llvm-svn: 323570
2018-01-26 22:02:52 +00:00
Richard Trieu 8610c9f43a Inline variable only used within assert.
llvm-svn: 323569
2018-01-26 21:55:13 +00:00
Krzysztof Parzyszek 90ca4e8b0c [Hexagon] Generate constant splats instead of loads from constant pool
llvm-svn: 323568
2018-01-26 21:54:56 +00:00
Davide Italiano 643b2b9e26 [lldbtestsuite] Don't crash on `None` input for is_exe().
Now the function returns `False`, and the caller can take the
appropriate action (in this case, for --executable, reporting
that the file doesn't exist).

llvm-svn: 323566
2018-01-26 21:46:10 +00:00
Wolfgang Pieb 6806cf9eb5 [DWARF] Temporarily removing test to make buildbots happy while investigating.
llvm-svn: 323564
2018-01-26 21:24:22 +00:00
Peter Collingbourne 939b16233b Fix the BinaryPredicate form of std::is_permutation to not rely on operator==
According to [1], forms 2 and 4 of std::is_permutation should use the passed in
binary predicate to compare elements. operator== should only be used for forms
1 and 3 which do not take a binary predicate.

This CL fixes forms 2 and 4 which relied on operator== for some comparisons.

[1] http://en.cppreference.com/w/cpp/algorithm/is_permutation

Patch by Thomas Anderson!

Differential Revision: https://reviews.llvm.org/D42518

llvm-svn: 323563
2018-01-26 21:23:27 +00:00
Krzysztof Parzyszek d4273abb69 [Hexagon] Make sure that offset on globals matches alignment requirements
A correctly aligned address may happen to be separated into a variable
part and a constant part, where the constant part does not match the
alignment needed in a load/store that uses this address. Such a constant
cannot be used as an immediate offset in an indexed instruction.

When lowering a global address, make sure that if there is an offset
folded into the global, the offset is valid for all uses in load/store
instructions.

llvm-svn: 323562
2018-01-26 21:20:04 +00:00
Krzysztof Parzyszek 95614acc24 [Hexagon] Replace multiple vector extracts with store-load combinations
llvm-svn: 323561
2018-01-26 21:17:14 +00:00
Wolfgang Pieb 06c0eca3c0 [DWARF] Temporarily removing a test that caused an independent failure on the mingw target.
Will recommit once that is addressed.

llvm-svn: 323560
2018-01-26 20:47:24 +00:00
Eli Friedman 29108843ff [LivePhysRegs] Preserve pristine regs in blocks with no successors.
One common source of blocks with no successors is calls to noreturn
functions; we want to preserve pristine registers in case they throw an
exception.

The whole pristine register thing is messy (we should really prefer to
explicitly model registers), but this fills a hole in the model for now.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36073.

Differential Revision: https://reviews.llvm.org/D42509

llvm-svn: 323559
2018-01-26 20:23:00 +00:00
Benjamin Kramer d15b2898d3 [Support] Move PrintEscapedString into the library its declaration is in
llvm-svn: 323558
2018-01-26 20:21:02 +00:00
Benjamin Kramer a03d3198ee [X86] Unbreak the build.
X86ISelLowering.cpp:34130:5: error: return type 'llvm::SDValue' must
match previous return type 'const llvm::SDValue' when lambda expression
has unspecified explicit return type

llvm-svn: 323557
2018-01-26 20:16:43 +00:00
Alexey Bataev 7ad4e31c3b [SLP] Test for trunc vectorization, NFC.
llvm-svn: 323556
2018-01-26 20:07:55 +00:00
Craig Topper d4795b700d [X86] Allow any_extend to be combined with setcc on VLX targets.
For VLX target getSetccResultType returns vXi1 which prevents the target independent DAG combine from doing this tranform itself.

llvm-svn: 323555
2018-01-26 20:02:52 +00:00
Benjamin Kramer 4bb33349a6 Try to unbreak 32 bit builds after r323528.
llvm-svn: 323554
2018-01-26 20:01:13 +00:00
Simon Pilgrim 8e9becbd81 [X86][AVX512] Add combining support for X86ISD::VTRUNCS
Similar to the existing support for X86ISD::VTRUNCUS.

Differential Revision: https://reviews.llvm.org/D42544

llvm-svn: 323553
2018-01-26 20:01:12 +00:00
Craig Topper ace5c37c57 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323552
2018-01-26 19:34:45 +00:00
Craig Topper 8f324bb1a4 [SelectionDAGISel] Add a debug print before call to Select. Adjust where blank lines are printed during isel process to make things more sensibly grouped.
Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table.

It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search.

There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line.

llvm-svn: 323551
2018-01-26 19:34:20 +00:00
Craig Topper b207dd6870 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323550
2018-01-26 19:34:14 +00:00
Argyrios Kyrtzidis 71b74ebb1e [index] Fix crash when indexing a C++14 PCH/module related to TemplateTemplateParmDecls of alias templates
TemplateTemplateParmDecls of alias templates ended-up serialized as 'file-level decls' which was causing a crash while trying to index a PCH/module file that contained them.
Commit makes sure TemplateTemplateParmDecls are not recorded as such kind of decls.

Fixes crash of rdar://36608297

Differential Revision: https://reviews.llvm.org/D42588

llvm-svn: 323549
2018-01-26 19:26:12 +00:00
Krzysztof Parzyszek 1a1edbfb04 [Hexagon] Fix an incorrect assertion in HexagonConstExtenders
llvm-svn: 323548
2018-01-26 19:20:50 +00:00
Saleem Abdulrasool f591e36b89 AST: support protocol conformances on id/class/interfaces in MS ABI
Add support for mangling ObjC protocol conformances in MS ABI as if they are
COM interfaces. By diverging from the itanium mangling of `objc_protocol`
prefixed names, this approach allows for a semi-reasonable, albeit of
questionable sanity, undecoration via existing tooling. There is also the
possibility of adding an extension and taking part of the namespace to add the
conformance via the `L` and `Z` "modifiers", but the existing tooling would not
be able to properly undecorated the symbol even though incidentally `undname`
currently produces something legible while wine's implementation is not able to
cope with the extension.

This allows for the disambiguation of overloads where the parameter differs
only in the protocol conformance of the ObjC type, e.g.

```
@protocol P;
void f(std::vector<id>);
void f(std::vector<id<P>>);
```

which clang would previously fail due to the mangling being identical as the
protocol conformance was ignored.

llvm-svn: 323547
2018-01-26 19:08:26 +00:00
Wolfgang Pieb 456b555ffe [DWARF] Generate DWARF v5 string offsets tables along with strx* index forms.
Summary: This is the producer side for DWARF v5 string offsets tables. The reader/consumer
side was committed with r321295. All compile and type units in a module share a 
contribution to the string offsets table. Indirect strings use the strx{1,2,3,4} index forms.

Reviewers: dblaikie, aprantl, JDevliegehere

Differential Revision: https://reviews.llvm.org/D42021

llvm-svn: 323546
2018-01-26 18:52:58 +00:00
Sanjay Patel b8ae262bd3 [x86] fix typo in comment; NFC
llvm-svn: 323545
2018-01-26 18:44:32 +00:00
Matt Davis b6616ae662 [NFC] Remove apostrophe to use 'it' in the possessive form.
Summary: This is  a simple change to test commit access with.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42586

llvm-svn: 323544
2018-01-26 18:43:57 +00:00
Craig Topper 3672f00e01 [X86] Define __IBT__ when -mibt is specified.
llvm-svn: 323543
2018-01-26 18:31:14 +00:00
Simon Pilgrim 1b14bdc0b8 [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to v4i32/v4f32
Extension to D42431, adding support for v4i32/v4f32 as well as v2i64/v2f64 now that D42308 has landed

llvm-svn: 323542
2018-01-26 17:19:59 +00:00
Simon Pilgrim 76ede609f6 [X86][SSE] Don't colaesce v4i32 extracts
We currently coalesce v4i32 extracts from all 4 elements to 2 v2i64 extracts + shifts/sign-extends.

This seems to have been added back in the days when we tended to spill vectors and reload scalars, or ended up with repeated shuffles moving everything down to 0'th index. I don't think either of these are likely these days as we have better EXTRACT_VECTOR_ELT and VECTOR_SHUFFLE handling, and the existing code tends to make it very difficult for various vector and load combines.

Differential Revision: https://reviews.llvm.org/D42308

llvm-svn: 323541
2018-01-26 17:11:34 +00:00
Simon Pilgrim d567c27c84 [X86][SSE] Drop PMADDWD in lowerMul
As mentioned in D42258, we don't need this any more

llvm-svn: 323540
2018-01-26 16:57:36 +00:00
Nirav Dave 9896238dc9 [DAG] Teach findBaseOffset to interpret indexes of indexed memory operations
Indexed outputs are addition / subtractions and can be interpreted as such.

llvm-svn: 323539
2018-01-26 16:51:27 +00:00