implementation of a Target{RegInfo, InstrInfo, Machine, etc} now has a separate
header and a separate implementation file.
This means that instead of a massive SparcInternals.h that forces a
recompilation of the whole target whenever a minor detail is changed, you should
only recompile a few files.
Note that SparcInternals.h is still around; its contents should be minimized.
llvm-svn: 10500
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
llvm-svn: 10461
* There is now only one pass to print out assembly instead of two
* It is a FunctionPass
* The Module-level printing of globals is now in doFinalization() method of the
FunctionPass
* The code has been reformatted to follow LLVM coding standards
* Some comments, not all, were doxygenified
* Last but not least, the function to create an instance of this pass is also no
longer a method in the UltraSparc class.
llvm-svn: 9953
for the Sparc backend: breaking up constant expressions. Thus, we cannot have it
guarded by a conditional, it should never be disabled.
Also, it's now available for the JIT since it is a FunctionPass.
llvm-svn: 9791
MachineConstantPool. This involved refactoring the two classes involved in
printing out Sparc assembly. In fact, they should share all this code anyway.
llvm-svn: 9776
it will be converted to a MachineConstantPool index during instruction
selection
* This is now eligible to become a FunctionPass since it does not have any side
effects outside of the function it is processing.
llvm-svn: 9773
* It's no longer a BasicBlock pass: update comment on run() method
* Fix placement of braces to be consistent
* Delete extraneous whitespace
llvm-svn: 9361
the module. This change converts it from being a basic block pass to being
a simple pass. This allows elimination of the annotation and simplification
of the logic for moving constants into global variables.
llvm-svn: 9320
Make insertFarJumpAtAddr() return void, because nothing uses its return value.
Remove some commented-out code.
Implement replaceMachineCodeForFunction() for SPARC.
llvm-svn: 9203
Rename SlotCalculator::getValSlot() to SlotCalculator::getSlot(),
SlotCalculator::insertValue() to SlotCalculator::getOrCreateSlot(),
SlotCalculator::insertVal() to SlotCalculator::insertValue(), and
SlotCalculator::doInsertVal() to SlotCalculator::doInsertValue().
llvm-svn: 9190
functionality of FunctionInfo pass as doFinalization method.
Rename pass to match names of other passes like it.
Rename the pass creator fn to mimic the other creator fn names.
Include StringExtras for utostr().
Make symbol prologue/epilogue stuff redundant with
EmitBytecodeToAssembly, in preparation for refactoring.
llvm-svn: 8597
some confusion when trying to generate files (it probably couldn't tell that
./file and $(SourceDir)/file may be the same file).
Now, just let VPATH find everything, and list the primary tblgen file first in
the list of dependencies so that we can just use $< to reference it in the make
rule.
This should hopefully fix the nightly tester.
llvm-svn: 8433
much cleaner and easier.
Labeled .td as a suffix for tblgen files in Makefile.rules.
Modified build rules so that source files generated during the build are placed
in the build directory and not the source directory (and not in a Debug
directory). This makes the system cleaner and allows us to have a read-only
source tree.
llvm-svn: 8424
* Generate a single BA instead of 6-instruction JUMP if possible
(this occurs both in the creation and overwriting of the stub code)
* If possible, rewrite the ORIGINAL call to call the generated function
directly, thus bypassing the stub entirely
Also added some statistics on how often calls are overwritten and how often the
CompilationCallback is invoked.
llvm-svn: 8376
* Break apart saving and restoring registers into separate functions
* Instead of saving single and double FP registers, just save the double
registers -- aliasing helps preserve the single FP registers as well.
* Request just as much memory for a stub as we actually use
llvm-svn: 8200
registers are global, are NOT windowed, and hence can be clobbered!
* Removed unused register shorthand notations
* Fixed and cleaned up comments in inline assembly
llvm-svn: 7853
because saving i1 and i2 to their ``designated'' stack slots corrupts unknown
memory in other functions, standard libraries, and worse.
In addition, this has the benefit of improving JIT performance because we
eliminate writing out 4 instructions in CompilationCallback() and 2 loads and 2
stores.
llvm-svn: 7653
2. Handle fp-to-uint conversions directly here instead of relying on
a pre-transformation to replace them with the 2-step conversion.
3. Use size rather than explicitly checking types when deciding what
opcodes to use, wherever possible. This is less error prone (the
bug fix above was not the first time!).
4. Float-to-pointer casts shd now work though this hasn't been tested.
llvm-svn: 7645
* Doxygen-ified comments
* Added capability to make far calls (i.e., beyond 30 bits in CALL instr)
which implies that we need to delete function references that were added by
the call to addFunctionReference() because the actual call instruction is 10
instructions away (thanks to 64-bit address construction)
* Cleaned up code that generates far jumps by using an array+loop
SparcV9CodeEmitter.h:
* Explained more of the side-effects of emitFarCall()
llvm-svn: 7639
Note that some generated operators (like &, | or ^) may
not be supported by the assembler -- but if they've got
this far, it's better to generate them and let the assembler decide.
llvm-svn: 7476
since it is *necessary* for correct code generation. Only optional
transformations belong in the PreOpts pass (which needs to be renamed
from PreSelection to PreOpts).
llvm-svn: 7474
that depends on machine register size.
Moved insertCallerSavingCode() to PhyRegAlloc and
moved isRegVolatile and modifiedByCall to TargetRegInfo: they are all
machine independent. Remove several dead functions.
llvm-svn: 7392
Single and FP double reg types (which share the same reg class).
Now all methods marking/finding unused regs consider the regType
within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
llvm-svn: 7334
now works in instructions which require a 2-bit or 3-bit INTcc code.
Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.
llvm-svn: 7185
allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).
Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.
llvm-svn: 7178
* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
broken (because regTypes are broken)
llvm-svn: 7175
(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
llvm-svn: 7159
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
llvm-svn: 7151
correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.
This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.
llvm-svn: 7103
the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
llvm-svn: 7074
area to avoid using up precious stack space within the 4095 offset limit
from %fp. Such objects that would themselves live at a large offset
were being put there already so this is a simple change.
llvm-svn: 7066
deletes it, but we were merrily trying to fix the operands of that
instruction anyway! Instead, fix the replacement instruction.
(2) An Improvement: Check for and extract global values in all operands,
not just in known pointer operands. For example, they can occur in
call arguments, and probably other unforeseeable places as well.
This also eliminates the special-case handling of Load and Store.
llvm-svn: 7053
(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
MachineCodeForInstruction for the Call instruction.
*All* instructions generated by register allocation need to be
recorded in those maps, but it needs to be done uniformly.
llvm-svn: 7051
Move LowerAllocations, PrintFunction, and SymbolStripping passes, and
the corresponding -disable-strip and -d options, over here to the SPARC
target-specific bits of llc. Rename -d to -dump-asm.
tools/llc/Makefile:
Reindent. Add x86 library so that llc compiles again.
tools/llc/llc.cpp:
Remove support for running arbitrary optimization passes. Use opt instead.
Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted
above.
Allow user to select a backend (x86 or SPARC); default to guessing from
the endianness/pointer size of the input bytecode file.
Fix typos.
Delete empty .s file and exit with error status if target does not support
static compilation.
llvm-svn: 6776
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down
llvm-svn: 6652
Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
llvm-svn: 6619
Chris Lattner