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5 Commits

Author SHA1 Message Date
Daniel Sanders 683ed961e1 [mips] Work around inconsistency in llvm-mc's placement of fixup markers 
Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

llvm-svn: 209514
 2014-05-23 13:35:24 +00:00
Matheus Almeida 180d97dcdf [mips][msa] Update format of RUN lines for every MSA MC test. 
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.

llvm-svn: 197588
 2013-12-18 17:31:21 +00:00
Matheus Almeida a3aeed8c44 [mips][msa] Remove unneeded triple directive in MSA MC tests. 
No functional changes.

llvm-svn: 197559
 2013-12-18 11:06:13 +00:00
Matheus Almeida 50c6e82222 [mips][msa] Update encoding of bnz.v (typo). 
Note that there's no hardware yet that relies on that encoding.

llvm-svn: 195006
 2013-11-18 13:09:54 +00:00
Matheus Almeida eb68d9d985 [mips][msa] Direct Object Emission support for conditional branches. 
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
 2013-10-22 09:43:32 +00:00