02d126cb9d
[AVX512] add integer min/max intrinsics support.
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review:
http://reviews.llvm.org/D10439
llvm-svn: 239806
2015-06-16 08:39:27 +00:00
abe4a79b75
AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
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Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D10430
llvm-svn: 239694
2015-06-14 12:44:55 +00:00
00c9ad5ec2
AVX-512: Fixed a bug in comparison of i1 vectors.
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cmp eq should give kxnor instruction
cmp neq should give kxor
https://llvm.org/bugs/show_bug.cgi?id=23631
llvm-svn: 239460
2015-06-10 06:49:28 +00:00
00d9f8457b
AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
Differential Revision: http://reviews.llvm.org/D10310
llvm-svn: 239300
2015-06-08 14:03:17 +00:00
4078c75bd4
AVX-512: added all SKX forms of VPERMW/D/Q instructions.
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Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.
llvm-svn: 239016
2015-06-04 07:07:13 +00:00
402ebb34af
re-apply 238809
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AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991
llvm-svn: 238923
2015-06-03 13:41:48 +00:00
9e38086534
AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL.
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Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238917
2015-06-03 10:56:40 +00:00
8938f5acca
AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.
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Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238834
2015-06-02 14:12:54 +00:00
3425c932da
AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
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Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238811
2015-06-02 08:28:57 +00:00
8d897dd05f
revert 238809
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llvm-svn: 238810
2015-06-02 07:45:19 +00:00
17de10f37e
AVX-512: Implemented GETEXP instruction for KNL and SKX
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Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
llvm-svn: 238809
2015-06-02 07:18:14 +00:00
3582eb3b39
AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.
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Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238738
2015-06-01 11:05:34 +00:00
75ede68793
AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
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including encodings.
llvm-svn: 238729
2015-06-01 07:17:23 +00:00
42c96d9c0a
AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for encoding.
by Igor Breger (igor.breger@intel.com )
llvm-svn: 238728
2015-06-01 06:50:49 +00:00
86c7b46680
AVX-512: Fixed a bug in extracting subvector from v64i1
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By Igor Breger (igor.breger@intel.com )
llvm-svn: 238322
2015-05-27 14:09:33 +00:00
3948c590e3
AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238301
2015-05-27 08:15:19 +00:00
f61727d880
AVX-512: fixed algorithm of building vectors of i1 elements
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fixed extract-insert i1 element,
load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage.
added a bunch of new tests.
llvm-svn: 237793
2015-05-20 14:32:03 +00:00
08ce53c0ea
AVX-512: Added patterns for scalar-to-vector broadcast
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llvm-svn: 237558
2015-05-18 07:06:23 +00:00
ad9c396838
AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set
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Added encoding tests.
llvm-svn: 237557
2015-05-18 06:42:57 +00:00
1d6a495d6d
AVX-512: fixed a bug in mask operations - (i1 1) pattern
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Filling k-reg with all-ones value was wrong,
(i1 1) should switch on only one bit in mask register
llvm-svn: 237536
2015-05-17 07:28:51 +00:00
1b2f2f1b37
AVX-512: fixed a bug in encoding of VPSRAQ instrcution,
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added a bunch of encoding tests.
llvm-svn: 237232
2015-05-13 07:35:05 +00:00
0d7e9364d1
AVX-512: Added SKX instructions and intrinsics:
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{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236971
2015-05-11 06:05:05 +00:00
75d1489326
AVX-512: fixed a bug in i1 vectors lowering
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llvm-svn: 236947
2015-05-10 10:33:32 +00:00
29792e9a80
AVX-512: Added all forms of FP compare instructions for KNL and SKX.
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Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 236714
2015-05-07 11:24:42 +00:00
60eb9db7bb
AVX-512: added calling convention for i1 vectors in 32-bit mode.
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Fixed some bugs in extend/truncate for AVX-512 target.
Removed VBROADCASTM (masked broadcast) node, since it is not used any more.
llvm-svn: 236420
2015-05-04 12:40:50 +00:00
52266388f8
AVX-512: added integer "add" and "sub" instructions with saturation for SKX
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with intrinsics and tests
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236418
2015-05-04 12:35:55 +00:00
2557a22be7
AVX-512: Added VPACK* instructions forms for KNL and SKX
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and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236414
2015-05-04 09:14:02 +00:00
e1eda8a9e6
Masked gather and scatter - added DAGCombine visitors
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and AVX-512 instruction selection patterns.
All other patches, including tests will follow.
http://reviews.llvm.org/D7665
llvm-svn: 236211
2015-04-30 08:38:48 +00:00
d1084c5b3f
AVX-512: Extend/Truncate operations for SKX,
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SETCC for bit-vectors
llvm-svn: 235875
2015-04-27 12:57:59 +00:00
0e6d6d54ce
AVX-512: Added VPMOVx2M instructions for SKX,
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fixed encoding of VPMOVM2x.
llvm-svn: 235385
2015-04-21 14:38:31 +00:00
431b81e41f
AVX-512: Added VPTESTM and VPTESTNM instructions for SKX
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llvm-svn: 235383
2015-04-21 13:13:46 +00:00
50b88ddb87
AVX-512: Added logical and arithmetic instructions for SKX
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by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 235375
2015-04-21 10:27:40 +00:00
1eeece1285
AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
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by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233906
2015-04-02 10:51:40 +00:00
d8fda62247
AVX-512: blank lines, duplicated tests, no functional changes
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see comments http://reviews.llvm.org/D6835
llvm-svn: 233528
2015-03-30 09:29:28 +00:00
72e3ccc375
AVX-512: Fixed the "commutative" property flag in VPANDN instruction
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By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233489
2015-03-29 09:14:29 +00:00
5d06b4c80c
AVX-512: Added encoding tests for VPROR, VPROL instructions,
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fixed opcode.
llvm-svn: 232018
2015-03-12 07:28:41 +00:00
0b9dbe33aa
AVX-512: Added SKX forms of shift instructions.
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Added rotation instructions, encoding only.
Added encoding tests for all these forms.
llvm-svn: 231916
2015-03-11 10:25:42 +00:00
de05f10de2
AVX-512, SKX: Enabled masked_load/store operations for this target.
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Added lowering for ISD::CONCAT_VECTORS and ISD::INSERT_SUBVECTOR for i1 vectors,
it is needed to pass all masked_memop.ll tests for SKX.
llvm-svn: 231371
2015-03-05 15:11:35 +00:00
d207f17fa1
AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes.
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No functional changes.
llvm-svn: 231069
2015-03-03 15:03:35 +00:00
2689d78909
AVX-512: Simplified MOV patterns, no functional changes.
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llvm-svn: 230954
2015-03-02 12:46:21 +00:00
09b27e7b24
[X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743.
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llvm-svn: 230924
2015-03-02 00:22:29 +00:00
0995479e67
Reverted 230471 - gather scatter handling in table gen.
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llvm-svn: 230892
2015-03-01 08:23:41 +00:00
02ffd26023
AVX-512: Added mask and rounding mode for scalar arithmetics
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Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.
llvm-svn: 230891
2015-03-01 07:44:04 +00:00
56eadcf5ce
AVX-512: Gather and Scatter patterns
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Gather and scatter instructions additionally write to one of the source operands - mask register.
In this case Gather has 2 destination values - the loaded value and the mask.
Till now we did not support code gen pattern for gather - the instruction was generated from
intrinsic only and machine node was hardcoded.
When we introduce the masked_gather node, we need to select instruction automatically,
in the standard way.
I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands.
(Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big
patch in many small patches)
llvm-svn: 230471
2015-02-25 09:46:31 +00:00
52e81bc499
AVX-512: recommitted 229837 + bugfix + test
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llvm-svn: 230223
2015-02-23 15:12:31 +00:00
0d94fa98e5
Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics."
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The instructions were being generated on architectures that don't support avx512.
This reverts commit r229837.
llvm-svn: 229942
2015-02-20 00:45:28 +00:00
06b32cdfed
Add a license header to the AVX512 file.
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llvm-svn: 229941
2015-02-20 00:36:53 +00:00
69e8b45b13
AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics.
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llvm-svn: 229837
2015-02-19 10:48:04 +00:00
714f23bcdb
AVX-512: Added support for FP instructions with embedded rounding mode.
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By Asaf Badouh <asaf.badouh@intel.com>
llvm-svn: 229645
2015-02-18 07:59:20 +00:00
ba84672519
AVX-512: changes in intel_ocl_bi calling conventions
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- added mask types v8i1 and v16i1 to possible function parameters
- enabled passing 512-bit vectors in standard CC
- added a test for KNL intel_ocl_bi conventions
llvm-svn: 229482
2015-02-17 09:20:12 +00:00
Asaf Badouh