Commit Graph

285745 Commits

Author SHA1 Message Date
Sanjay Patel d189b596ae [InstCombine] regenerate test checks; NFC
llvm-svn: 328325
2018-03-23 15:19:35 +00:00
Simon Pilgrim 1335b9c0ca [X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function units
llvm-svn: 328324
2018-03-23 15:17:50 +00:00
Sanjay Patel 713ca3d36a [InstCombine] reduce code duplication; NFC
llvm-svn: 328323
2018-03-23 15:07:35 +00:00
Sanjay Patel 6de89ce3f7 [InstCombine] improve variable name; NFC
llvm-svn: 328322
2018-03-23 14:48:31 +00:00
John Brawn e3b44f9de6 [AArch64] Don't reduce the width of loads if it prevents combining a shift
Loads and stores can only shift the offset register by the size of the value
being loaded, but currently the DAGCombiner will reduce the width of the load
if it's followed by a trunc making it impossible to later combine the shift.

Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and
make it prevent the width reduction if this is what would happen, though do
allow it if reducing the load width will let us eliminate a later sign or zero
extend.

Differential Revision: https://reviews.llvm.org/D44794

llvm-svn: 328321
2018-03-23 14:47:07 +00:00
Simon Pilgrim 5792e10ffb [X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructions
This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops.

llvm-svn: 328320
2018-03-23 14:45:03 +00:00
George Rimar 16f11462ce [ELF] - Simplify. NFC.
llvm-svn: 328319
2018-03-23 14:43:51 +00:00
Simon Pilgrim 8619962c73 [X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instructions to correctly use JFPU1 scheduler pipe followed by JLAGU/JSAGU/JFPA/JVALU function units
Fixes throughput to match Agner/Fam16h-SoG as well.

llvm-svn: 328318
2018-03-23 14:27:26 +00:00
Daniel Neilson a0c5f3eff1 Remove the deprecated single-alignment IRBuilder API for memcpy/memmove (NFC)
Summary:
This change is part of step six in the series of changes to remove the alignment
argument from memcpy/memmove/memset in favour of alignment attributes. At this
point all users of the IRBuilder APIs for creating a memcpy/memmove call given
a single value for alignment have been updated. We want to discourage usage of
these old APIs in favour of the newer ones that allow for separate source and
destination alignments, so this patch deletes the old API.

Specifically, we remove from IRBuilder:
CallInst *CreateMemCpy(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
                       bool isVolatile = false, MDNode *TBAATag = nullptr,
                       MDNode *TBAAStructTag = nullptr,
                       MDNode *ScopeTag = nullptr,
                       MDNode *NoAliasTag = nullptr)
CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Align,
                       bool isVolatile = false, MDNode *TBAATag = nullptr,
                       MDNode *TBAAStructTag = nullptr,
                       MDNode *ScopeTag = nullptr,
                       MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
                        bool isVolatile = false, MDNode *TBAATag = nullptr,
                        MDNode *ScopeTag = nullptr,
                        MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Align,
                        bool isVolatile = false, MDNode *TBAATag = nullptr,
                        MDNode *ScopeTag = nullptr,
                        MDNode *NoAliasTag = nullptr)

Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.

Reference
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

llvm-svn: 328317
2018-03-23 14:25:35 +00:00
Matthew Simpson 6c289a1c74 [SLP] Stop counting cost of gather sequences with multiple uses
When building the SLP tree, we look for reuse among the vectorized tree
entries. However, each gather sequence is represented by a unique tree entry,
even though the sequence may be identical to another one. This means, for
example, that a gather sequence with two uses will be counted twice when
computing the cost of the tree. We should only count the cost of the definition
of a gather sequence rather than its uses. During code generation, the
redundant gather sequences are emitted, but we optimize them away with CSE. So
it looks like this problem just affects the cost model.

Differential Revision: https://reviews.llvm.org/D44742

llvm-svn: 328316
2018-03-23 14:18:27 +00:00
Daniel Neilson a92bcbb2c8 Remove deprecated MemIntrinsic methods (NFC)
Summary:
This change is part of step six in the series of changes to remove
the alignment argument from memcpy/memmove/memset in favour of
alignment attributes. At this point all uses of
MemIntrinsicInst::[get|set]Alignment() have been updated, so we now
remove these methods entirely to discourage their use.

Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.

Reference
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

llvm-svn: 328315
2018-03-23 14:02:54 +00:00
Alexey Bataev bff360865b [DEBUGINFO] Add flag for DWARF2 to use sections as references.
Summary:
Some targets does not support labels inside debug sections, but support
references in form `section+offset`. Patch adds initial support
for this.

Reviewers: echristo, probinson, jlebar

Subscribers: llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D43943

llvm-svn: 328314
2018-03-23 13:35:54 +00:00
Christof Douma 4a025cc79d [ARM] Support float literals under XO
When targeting execute-only and fp-armv8, float constants in a compare
resulted in instruction selection failures. This is now fixed by using
vmov.f32 where possible, otherwise the floating point constant is
lowered into a integer constant that is moved into a floating point
register.

This patch also restores using fpcmp with immediate 0 under fp-armv8.

Change-Id: Ie87229706f4ed879a0c0cf66631b6047ed6c6443
llvm-svn: 328313
2018-03-23 13:02:03 +00:00
Florian Hahn f73c3ece7f Revert r328307: [IPSCCP] Use constant range information for comparisons of parameters.
Reverted for now, due to it causing verifier failures.

llvm-svn: 328312
2018-03-23 12:49:39 +00:00
Amara Emerson f542355942 [GlobalISel] Fix legalizer combine to not use illegal input G_EXTRACT.
This was being masked because GISel is enabled by default for -O0 and
the abort was disabled. Modified test to explicitly enable abort.

llvm-svn: 328311
2018-03-23 12:48:57 +00:00
Matthew Simpson 4316a2623a [test] Allow for optional No-Op Barrier Pass in O0 pipeline
llvm-svn: 328310
2018-03-23 12:47:54 +00:00
Simon Pilgrim 9ea14bbbb0 [X86][Znver1] Fix instregex entries that don't match any instructions (D44687)
Reviewed by @GGanesh and @craig.topper

llvm-svn: 328309
2018-03-23 12:08:23 +00:00
Simon Pilgrim 2755893834 [X86][SandyBridge] Fix missing comma that was causing string concatenation of 2 instregex entries
Found while updating D44687

llvm-svn: 328308
2018-03-23 11:56:38 +00:00
Florian Hahn b1feec087e [IPSCCP] Use constant range information for comparisons of parameters.
For comparisons with parameters, we can use the ParamState lattice
elements which also provide constant range information. This improves
the code for PR33253 further and gets us closer to use
ValueLatticeElement for all values.

Also, as we are using the range information in the solver directly, we
do not need tryToReplaceWithConstantRange afterwards anymore.

Reviewers: dberlin, mssimpso, davide, efriedma

Reviewed By: mssimpso

Differential Revision: https://reviews.llvm.org/D43762

llvm-svn: 328307
2018-03-23 11:56:00 +00:00
Andrea Di Biagio b5088da452 [llvm-mca] Pass the InstrBuilder to the constructor of Backend.
This is done in preparation for the fix for PR36784.
No functional change.

llvm-svn: 328306
2018-03-23 11:50:43 +00:00
Andrea Di Biagio 29538c6ddb [llvm-mca] Add flag -resource-pressure to enable/disable printing of the resource pressure view.
By default, the tool always enables the resource pressure view.
This flag lets user specify whether they want to add that view or not.

llvm-svn: 328305
2018-03-23 11:33:09 +00:00
Simon Pilgrim a1e3ea01ef [X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler pipe and JFPX/JVALU function unit as well as the AGUs
llvm-svn: 328304
2018-03-23 11:27:31 +00:00
Florian Hahn 588e640ea1 [AArch64] Clean-up a few over-eager regexps in models.
Patch by Simon Pilgrim <llvm-dev@redking.me.uk>

That is a slightly modified version of the AArch64 changes from
Simon's D44687 .

llvm-svn: 328303
2018-03-23 11:00:42 +00:00
Ilya Biryukov 976b6975e4 [clangd] Remove 'static' from a function inside anonymous ns. NFC
llvm-svn: 328302
2018-03-23 10:39:15 +00:00
Florian Hahn 52436a587e [LoopUnroll] Simplify induction variables after peeling too.
Loop peeling also has an impact on the induction variables, so we should
benefit from induction variable simplification after peeling too.

Reviewers: sanjoy, bogner, mzolotukhin, efriedma

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D43878

llvm-svn: 328301
2018-03-23 10:38:12 +00:00
Benjamin Kramer fbd4df2176 [ORC] Join materialization thread in unit test
There's are race between this thread and the destructor of the test ORC
components on the main threads. I saw flaky failures there in about 4%
of the runs of this unit test.

llvm-svn: 328300
2018-03-23 10:14:19 +00:00
George Rimar 54634f1990 [ELF] - Another fix for "LLD crashes with --emit-relocs when trying to proccess .eh_frame"
This fixes PR36367 which is about segfault when --emit-relocs is
used together with .eh_frame sections which happens because
of reordering of regular and .rel[a] sections.

Path changes loop that iterates over input sections to create
relocation target sections first.

Differential revision: https://reviews.llvm.org/D44679

llvm-svn: 328299
2018-03-23 09:18:31 +00:00
Martin Storsjo e1a64fe95c [ARM] Error out on .arm assembler directives on windows
Windows on arm is thumb only.

Differential Revision: https://reviews.llvm.org/D43005

llvm-svn: 328298
2018-03-23 09:10:03 +00:00
Martin Storsjo db75aa96d3 Revert "[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))"
This reverts commit r328252. This change broke building a number
of projects when targeting ARM and AArch64, see PR36873.

llvm-svn: 328297
2018-03-23 08:36:47 +00:00
Craig Topper dfeea84d63 [X86] Give VPCMPEQQ the same itinerary as its SSE counterpart.
llvm-svn: 328296
2018-03-23 06:58:55 +00:00
Craig Topper 4787b7f434 [X86] Correct the latencies of SNB integer vector multiplies based on Agner's data. Add missing MMX multiplies.
llvm-svn: 328295
2018-03-23 06:41:43 +00:00
Craig Topper 659c66dfc1 [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. Change pblendvb/blendvps/blendvpd to use WriteFVarBlend
llvm-svn: 328294
2018-03-23 06:41:41 +00:00
Craig Topper 7580a7997d [X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version.
llvm-svn: 328293
2018-03-23 06:41:40 +00:00
Craig Topper d5ac3ae8d3 [X86] Give VLDDQUrm and LDDQUrm the same itinerary.
llvm-svn: 328292
2018-03-23 06:41:39 +00:00
Craig Topper 7f142b8bf1 [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.
The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that.

llvm-svn: 328291
2018-03-23 06:41:38 +00:00
Craig Topper fae4173b47 [X86] Add VEXTRB/W/D/Q to Zen scheduler model.
The SSE versions were present, but not the VEX version.

llvm-svn: 328290
2018-03-23 06:41:36 +00:00
Craig Topper 6ef55d1887 [X86] Fix the itinerary for vextractps to match extractps.
llvm-svn: 328289
2018-03-23 06:41:35 +00:00
Rafael Espindola fe9a55a3f1 Bring r328238 back with a fix.
The issues was that we were setting hidden visibility if, when
processing a hidden class, we found out that we needed to emit a
reference to a vtable provided by the standard library.

Original message:

Set dso_local on vtables.

llvm-svn: 328288
2018-03-23 01:36:23 +00:00
Nirav Dave 5b3e8791b4 [DAG] Fix node id invalidation in Instruction Selection.
Invalidation should be bit negation. Add missing negation.

llvm-svn: 328287
2018-03-23 01:22:39 +00:00
Jordan Rose f040158de7 Remove problematic PrettyStackTrace entry added in r328276
I'm not sure /why/ this is causing issues for libclang, but it is.
Unbreak the buildbots since it's already consumed an hour of my time.

llvm-svn: 328286
2018-03-23 01:12:09 +00:00
Rafael Espindola 85e77b26be Fix the MSVC build.
llvm-svn: 328285
2018-03-23 00:42:47 +00:00
Rafael Espindola 3c3ebcc5f4 Fix PR36793.
With this patch lld will iterate over compile units to find the line
tables instead of assuming there is only one at offset 0.

llvm-svn: 328284
2018-03-23 00:35:27 +00:00
Volodymyr Sapsai 932d45ce4d [Modules] Update test to mention it requires C++14.
llvm-svn: 328283
2018-03-23 00:16:06 +00:00
George Karpenkov 2301c5ab4d [analyzer] Trust _Nonnull annotations for system framework
Changes the analyzer to believe that methods annotated with _Nonnull
from system frameworks indeed return non null objects.
Local methods with such annotation are still distrusted.
rdar://24291919

Differential Revision: https://reviews.llvm.org/D44341

llvm-svn: 328282
2018-03-23 00:16:03 +00:00
George Karpenkov 628920b460 [analyzer] Extend GCDAntipatternChecker to match group_enter/group_leave pattern
rdar://38480416

Differential Revision: https://reviews.llvm.org/D44653

llvm-svn: 328281
2018-03-23 00:16:02 +00:00
George Karpenkov 40b42a3ad8 [analyzer] [NFC] Move worklist implementation to WorkList.cpp
Current location is very confusing, especially because there is already
WorkList.h, and other code in CoreEngine.cpp is not related to work list
implementation.

Differential Revision: https://reviews.llvm.org/D44759

llvm-svn: 328280
2018-03-23 00:16:01 +00:00
Vitaly Buka c038b2f441 [sanitizer] Fix PPC bot
llvm-svn: 328279
2018-03-23 00:15:10 +00:00
Davide Italiano 7bbfd8a5b9 [CommandObjectFrame] Remove dead code.
llvm-svn: 328278
2018-03-23 00:14:41 +00:00
Abderrazek Zaafrani b5ac56fb81 [ARM] Add ARMv8.2-A FP16 vector intrinsic
Putting back the code in commit r327189 that was reverted in r322737. The code is being committed in three stages and this one is the last stage: 1) r327455 fp16 feature flags, 2) r327836 pass half type or i16 based on FullFP16, and 3) the code here which the front-end fp16 vector intrinsic for ARM.

Differential revision https://reviews.llvm.org/D43650

llvm-svn: 328277
2018-03-23 00:08:40 +00:00
Jordan Rose 1e879d8be6 Sink PrettyDeclStackTrace down to the AST library
...and add some very basic stack trace entries for module building.
This would have helped track down rdar://problem/38434694 sooner.

llvm-svn: 328276
2018-03-23 00:07:18 +00:00