3964059a16
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
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Sorry!
llvm-svn: 95892
2010-02-11 18:47:03 +00:00
34a6afc68d
Modified encoding bits specification for VFP instructions. In particular, the D
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bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
llvm-svn: 94855
2010-01-29 23:21:10 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
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llvm-svn: 91434
2009-12-15 17:24:14 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
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llvm-svn: 91305
2009-12-14 18:31:20 +00:00
098bd1bbea
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
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llvm-svn: 91143
2009-12-11 19:37:26 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
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llvm-svn: 91090
2009-12-11 01:42:04 +00:00
36d4dec28a
Thumb1 exception handling setjmp
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llvm-svn: 90246
2009-12-01 18:10:36 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
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This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
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VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
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{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
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ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
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llvm-svn: 89542
2009-11-21 06:21:52 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
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fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
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llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
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llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
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Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
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a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
772b2f84eb
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
68f495caad
Add missing encoding bits to NLdSt class of instructions.
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Patch by Johnny Chen.
llvm-svn: 84570
2009-10-20 00:19:08 +00:00
50820a2677
Add some instruction encoding bits for NEON load/store instructions.
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llvm-svn: 83490
2009-10-07 21:53:04 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
71140344f0
Fix double load / store multiple encoding.
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llvm-svn: 81403
2009-09-09 23:55:03 +00:00
9129376719
Expose the instruction contraint string as an argument to the NLdSt class.
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llvm-svn: 80011
2009-08-25 17:46:06 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
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llvm-svn: 78604
2009-08-10 22:17:39 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
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llvm-svn: 78101
2009-08-04 20:39:05 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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llvm-svn: 78081
2009-08-04 17:53:06 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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llvm-svn: 77242
2009-07-27 19:59:26 +00:00
a0b2dc93b5
Fix typo in addrmode definition.
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llvm-svn: 76806
2009-07-22 22:24:31 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
81cdd21dcb
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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llvm-svn: 75254
2009-07-10 17:03:29 +00:00
5edd90cbbc
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
f731a2df6b
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
14965760a7
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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llvm-svn: 74988
2009-07-08 01:46:35 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
d76f0be844
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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llvm-svn: 74158
2009-06-25 02:08:06 +00:00
bec1dba896
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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llvm-svn: 73985
2009-06-23 19:38:13 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
fabdcce677
Handle the rest of pseudo instructions.
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llvm-svn: 59275
2008-11-13 23:36:57 +00:00
Johnny Chen