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16 Commits

Author SHA1 Message Date
Krzysztof Parzyszek f97fdf5792 [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX 
llvm-svn: 372616
 2019-09-23 14:33:27 +00:00
Krzysztof Parzyszek ac83aab035 [Hexagon] Generate min/max instructions for 64-bit vectors 
llvm-svn: 369124
 2019-08-16 16:16:27 +00:00
Krzysztof Parzyszek 8460301d58 [Hexagon] Generate vector min/max for HVX 
llvm-svn: 369014
 2019-08-15 16:13:17 +00:00
Krzysztof Parzyszek d8b780dcd6 [Hexagon] Remove 'T' from HasVNN predicates, NFC 
Patch by Sumanth Gundapaneni.

llvm-svn: 335124
 2018-06-20 13:56:09 +00:00
Krzysztof Parzyszek c1e712baa5 [Hexagon] Implement vector-pair zero as V6_vsubw_dv 
llvm-svn: 334123
 2018-06-06 19:34:40 +00:00
Krzysztof Parzyszek aec2c0c9b6 [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ 
llvm-svn: 333760
 2018-06-01 14:52:58 +00:00
Krzysztof Parzyszek 840b02bccf [Hexagon] Add patterns for accumulating HVX compares 
llvm-svn: 333009
 2018-05-22 18:27:02 +00:00
Krzysztof Parzyszek f18009dbc6 [Hexagon] Fix the order of operands when selecting QCAT 
llvm-svn: 332526
 2018-05-16 21:02:43 +00:00
Krzysztof Parzyszek e8a0ae7346 [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns 
llvm-svn: 332525
 2018-05-16 21:00:24 +00:00
Krzysztof Parzyszek cff73a2118 [Hexagon] Add patterns for vector shift-and-accumulate 
llvm-svn: 331918
 2018-05-09 21:10:41 +00:00
Krzysztof Parzyszek 41a24b7b13 [Hexagon] Improve HVX instruction selection (bitcast, vsplat) 
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.

llvm-svn: 330471
 2018-04-20 19:38:37 +00:00
Krzysztof Parzyszek d92c37e090 [Hexagon] Generate code for vector bswap intrinsics 
llvm-svn: 330333
 2018-04-19 14:46:44 +00:00
Krzysztof Parzyszek 2c3edf0567 [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones 
This is a follow-up to r325169, this time for all types, not just HVX
vector types.

Disable this by default, since it's not always safe. 

llvm-svn: 326915
 2018-03-07 17:27:18 +00:00
Krzysztof Parzyszek ad83ce4cb4 [Hexagon] Split HVX vector pair loads/stores, expand unaligned loads 
llvm-svn: 325169
 2018-02-14 20:46:06 +00:00
Krzysztof Parzyszek 9b48e8d233 [Hexagon] Add code to select QTRUE and QFALSE 
Fixes http://llvm.org/PR36320.

llvm-svn: 324763
 2018-02-09 19:10:46 +00:00
Krzysztof Parzyszek 8abaf8954a [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC 
llvm-svn: 324392
 2018-02-06 20:22:20 +00:00