8b3deabd2d
Revert r146822 at Pete Cooper's request as it broke clang self hosting.
...
Hope I did this correctly :)
llvm-svn: 146834
2011-12-17 19:48:52 +00:00
eadf124d2b
SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
...
For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/10554090>
llvm-svn: 146822
2011-12-17 06:32:38 +00:00
3c2848ea31
Deleting the json-bench-test until I understand why it is flaky.
...
llvm-svn: 146821
2011-12-17 06:29:32 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
...
asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
...
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
518cda42b9
The powers that be have decided that LLVM IR should now support 16-bit
...
"half precision" floating-point with a first-class type.
This patch adds basic IR support (but not codegen support).
llvm-svn: 146786
2011-12-17 00:04:22 +00:00
27886c6c1e
When recursing for the original size of a type, stop if we are at a
...
pointer or a reference type - we actually just want the size of the
pointer then for that.
Fixes rdar://10335756
llvm-svn: 146785
2011-12-16 23:42:45 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
...
Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2c899a181c
Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
...
llvm-svn: 146735
2011-12-16 13:09:10 +00:00
3fdf98c60f
By popular demand, link up types by name if they are isomorphic and one is an
...
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.
llvm-svn: 146728
2011-12-16 08:36:07 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
...
llvm-svn: 146726
2011-12-16 08:06:31 +00:00
561dade58d
[asan] add a test for instrumenting globals
...
llvm-svn: 146718
2011-12-16 01:28:19 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
...
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
...
llvm-svn: 146699
2011-12-15 22:56:33 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
918f976e66
Set specific target cpu for testcase.
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llvm-svn: 146678
2011-12-15 20:22:34 +00:00
2d6d3a2f96
Added test case for r146671.
...
llvm-svn: 146675
2011-12-15 19:56:07 +00:00
750366f014
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
...
llvm-svn: 146666
2011-12-15 17:59:23 +00:00
ef7b2f2532
Fix test.
...
llvm-svn: 146642
2011-12-15 04:52:47 +00:00
a45ab503f6
Make constant folding for GEPs a bit more aggressive.
...
llvm-svn: 146639
2011-12-15 04:33:48 +00:00
2ec824966d
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
...
llvm-svn: 146630
2011-12-15 02:07:20 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
b33c297f14
Added InstCombine for "select cond, ~cond, x" type patterns
...
These can be reduced to "~cond & x" or "~cond | x"
llvm-svn: 146624
2011-12-15 00:56:45 +00:00
16ad2905a3
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
...
llvm-svn: 146621
2011-12-15 00:50:34 +00:00
75d7d5e988
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
...
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
llvm-svn: 146610
2011-12-14 23:49:11 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
c268688643
Do not sink instruction, if it is not profitable.
...
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar 10266272.
llvm-svn: 146604
2011-12-14 23:20:38 +00:00
ad41ab5015
Improve the implementation of .incbin directive by replacing a loop by using
...
getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
llvm-svn: 146599
2011-12-14 22:34:45 +00:00
e0ced62119
LSR: Fold redundant bitcasts on-the-fly.
...
llvm-svn: 146597
2011-12-14 22:07:19 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
109f25c966
Add the .incbin directive which takes the binary data from a file and emits
...
it to the streamer. rdar://10383898
llvm-svn: 146592
2011-12-14 21:47:48 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
d7b2bb3bdd
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code size heuristics.
...
llvm-svn: 146578
2011-12-14 19:19:17 +00:00
bd944b4153
It turns out that clang does use pointer-to-function types to
...
point to ARC-managed pointers sometimes. This fixes rdar://10551239.
llvm-svn: 146577
2011-12-14 19:10:53 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
4020ae75ea
Add newline at EOF.
...
llvm-svn: 146538
2011-12-14 01:34:39 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
dce106940e
Test for 146516
...
llvm-svn: 146517
2011-12-13 21:06:59 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
7200123fa3
Add test/MC/Mips/dg.exp.
...
llvm-svn: 146472
2011-12-13 04:12:49 +00:00
341850fdc6
Move direct object emitter test to directory test/MC/Mips. Rename it to
...
elf-relsym.ll.
llvm-svn: 146470
2011-12-13 03:50:34 +00:00
e41963ce47
Relocation against a symbol, instead of against section. We had some extreme
...
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.
Patch by Jack Carter.
llvm-svn: 146468
2011-12-13 02:27:40 +00:00
86ffb03c79
Don't rely on a particular version string for llvm.
...
llvm-svn: 146456
2011-12-13 00:34:14 +00:00
525ca5fc69
Temporarily disable Hexagon tests. They are failing on OS X
...
llvm-svn: 146455
2011-12-13 00:33:45 +00:00
9e5908ae3a
Test case for r146432 by Jack Carter.
...
llvm-svn: 146433
2011-12-12 22:41:39 +00:00
fadc2c83e5
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
...
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
llvm-svn: 146417
2011-12-12 21:45:15 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
45c4164166
Only replace fwrite with fputc, if the return value is unused.
...
llvm-svn: 146411
2011-12-12 20:18:31 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
735cb8bcdc
Add support for gnu_indirect_function.
...
llvm-svn: 146377
2011-12-12 17:34:04 +00:00
6b0e34c445
Manually upgrade the test suite to specify the flag to cttz and ctlz.
...
I followed three heuristics for deciding whether to set 'true' or
'false':
- Everything target independent got 'true' as that is the expected
common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
set the flag in the way that exercises the most of codegen. For most
architectures this is also the likely path from a GCC builtin, with
'true' being set. It will (eventually) require lowering away that
difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
operation should be tested.
Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.
llvm-svn: 146370
2011-12-12 11:59:10 +00:00
f13db84794
Add an explicit test of the auto-upgrade functionality for the new
...
intrinsic syntax.
Now that this is explicitly covered, I plan to upgrade the existing test
suite to use an explicit immediate. Note that I plan to specify 'true'
in most places rather than the auto-upgraded value as that is the far
more common value to end up here as that is the value coming from GCC's
builtins. The only place I'm likely to put a 'false' in is when testing
x86 which actually has different instructions for the two variants.
llvm-svn: 146369
2011-12-12 11:23:11 +00:00
026cc37e48
Teach the verifier to reject all non-constant arguments to the second
...
argument of the cttz and ctlz intrinsics.
llvm-svn: 146360
2011-12-12 04:36:02 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
1d76d4196a
Don't assume things about the exact details of the LLVM version number,
...
such as what VCS information is attached.
llvm-svn: 146333
2011-12-10 21:40:31 +00:00
1c468af854
Revert associate SelectInsertValue test as well.
...
llvm-svn: 146332
2011-12-10 21:34:28 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
67a7f18faf
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
...
llvm-svn: 146318
2011-12-10 04:50:53 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
...
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
...
llvm-svn: 146299
2011-12-09 23:54:42 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
1d54d2210a
Update test to something more sensible.
...
llvm-svn: 146282
2011-12-09 21:54:10 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
dd998ff4df
[fast-isel] Add support for selecting insertvalue.
...
rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
...
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
...
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
d04d152998
Add -unroll-runtime for unrolling loops with run-time trip counts.
...
Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
llvm-svn: 146245
2011-12-09 06:19:40 +00:00
5895fa79d6
Forgot setting -march.
...
llvm-svn: 146244
2011-12-09 06:15:00 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
...
symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
053a724483
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
...
llvm-svn: 146219
2011-12-09 01:16:26 +00:00
fe970725cc
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
...
trivially infinite.
llvm-svn: 146197
2011-12-08 22:36:35 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
...
llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
3a97d946d2
Tidy up a bit.
...
llvm-svn: 146190
2011-12-08 22:04:40 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
...
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
27a33edfa0
Tidy up a bit.
...
llvm-svn: 146181
2011-12-08 20:53:19 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
3294538546
Add test for r146163.
...
llvm-svn: 146167
2011-12-08 19:21:39 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
0faa233439
test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.
...
llvm-svn: 146152
2011-12-08 15:24:09 +00:00
26edb291ac
Fix a bug in the integer-promotion of bitcast operations on vector types.
...
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
llvm-svn: 146150
2011-12-08 13:10:01 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
5ff64c7141
Tidy up.
...
llvm-svn: 146113
2011-12-08 00:41:54 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
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llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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llvm-svn: 146039
2011-12-07 17:51:15 +00:00
a4337ced68
Tidy up. Move MachO tests to MachO directory.
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llvm-svn: 146038
2011-12-07 17:50:28 +00:00
ed8b3e38ec
Support vector bitcasts in the AsmPrinter. PR11495.
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llvm-svn: 146001
2011-12-07 00:50:54 +00:00
0e58cba286
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
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llvm-svn: 145996
2011-12-07 00:11:56 +00:00
0fc34bc2d3
delaying restore-cr changed assigned registers in some tests
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llvm-svn: 145963
2011-12-06 20:55:46 +00:00
0702bc1b28
add a test case that uses RESTORE_CR
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llvm-svn: 145962
2011-12-06 20:55:41 +00:00
04424665c3
PTX: Continue to fix up the register mess.
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llvm-svn: 145947
2011-12-06 17:39:48 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
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llvm-svn: 145927
2011-12-06 09:04:59 +00:00
51416d5f00
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
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llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
5bdc0fbabd
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
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MC/MachO assumes x86.
llvm-svn: 145916
2011-12-06 03:56:05 +00:00
5df9096584
LSR: prune undesirable formulae early.
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It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
llvm-svn: 145906
2011-12-06 03:13:31 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
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Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
8abf65a130
Probably not a good idea to convert a single vector load into a memcpy. We
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don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
llvm-svn: 145879
2011-12-06 00:19:08 +00:00
19446a07a7
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
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where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
llvm-svn: 145865
2011-12-05 22:37:00 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
8b5e92577b
Update tests for r145860. Add a few new ones.
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llvm-svn: 145861
2011-12-05 22:21:28 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
97a6028b3a
Add test case - this input used to crash because of duplicate generation of SPILL_CRs
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llvm-svn: 145820
2011-12-05 17:55:22 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
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llvm-svn: 145819
2011-12-05 17:55:17 +00:00
e18c72689c
remove wasted space for extra bit copies of CR2 subregs
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llvm-svn: 145817
2011-12-05 17:55:06 +00:00
e6efe405de
test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.
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llvm-svn: 145805
2011-12-05 07:54:57 +00:00
3924cb0267
Add support for vectors of pointers.
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llvm-svn: 145801
2011-12-05 06:29:09 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
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AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
Kevin Enderby