e95f391ef1
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
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all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
3243e10ef0
Add 64-bit jmp instructions to the list of instructions that
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can terminate a block with no fall-through.
llvm-svn: 42029
2007-09-17 15:19:08 +00:00
48ea03d169
Add patterns for SHLD64* and SHRD64*.
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llvm-svn: 41975
2007-09-14 23:17:45 +00:00
483e1ce16e
Add implicit def of EFLAGS on those instructions that may modify flags.
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llvm-svn: 41962
2007-09-14 21:48:26 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
189df733ed
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:
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leal (,%rcx,8), %rcx
It should be
leal (,%rcx,8), %ecx
llvm-svn: 41735
2007-09-06 00:14:41 +00:00
d36d30b53c
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.
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llvm-svn: 41007
2007-08-10 21:18:25 +00:00
936d17aa1b
Don't pollute the meaning of isUnpredicatedTerminator.
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llvm-svn: 40537
2007-07-26 17:32:14 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
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llvm-svn: 37960
2007-07-06 23:22:03 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
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their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
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model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
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llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
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implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
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llvm-svn: 37266
2007-05-21 18:44:17 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37193
2007-05-18 00:18:17 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
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llvm-svn: 36430
2007-04-25 07:12:14 +00:00
e2324ca17d
Remove some invalid instructions from this check.
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llvm-svn: 36404
2007-04-24 21:17:46 +00:00
ac5b650a54
Adding more MMX instructions.
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llvm-svn: 35638
2007-04-03 23:48:32 +00:00
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
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llvm-svn: 35616
2007-04-03 06:00:37 +00:00
bcd38852f2
Compile CodeGen/X86/lea-3.ll:test2 to:
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_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret
instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret
llvm-svn: 35434
2007-03-28 18:12:31 +00:00
c56e4920d2
Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the
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system assembler not groking legal instructions like "leal (,%esi,8), %ecx".
llvm-svn: 35393
2007-03-28 00:58:40 +00:00
3e1d917e80
Two changes:
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1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2 , #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
llvm-svn: 35204
2007-03-20 06:08:29 +00:00
6092ce25cf
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
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moves, loads, etc. are recognized.
llvm-svn: 35031
2007-03-08 22:09:11 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
07fc107e90
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.
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llvm-svn: 32097
2006-12-01 21:52:41 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
7ae482c52a
Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.
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llvm-svn: 31794
2006-11-16 23:22:26 +00:00
dc2c8748a7
Properly transfer kill / dead info.
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llvm-svn: 31765
2006-11-15 20:58:11 +00:00
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
7443600ef8
fix wonky indentation
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llvm-svn: 31298
2006-10-30 22:27:23 +00:00
53ebf20c26
add another target hook for branch folding.
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llvm-svn: 31262
2006-10-28 17:29:57 +00:00
3a897f31fa
Implement support for branch condition reversal.
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llvm-svn: 31099
2006-10-21 05:52:40 +00:00
d881660366
Simplify code, no functionality change
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llvm-svn: 31097
2006-10-21 05:42:09 +00:00
6fca75ec05
allow insertion of a conditional branch with fall-through
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llvm-svn: 31095
2006-10-21 05:34:23 +00:00
20e75d4635
update assert message
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llvm-svn: 31093
2006-10-21 04:42:29 +00:00
8366b874a9
bugfix
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llvm-svn: 31074
2006-10-20 20:44:34 +00:00
c0fb567e23
Implement branch analysis/xform hooks required by the branch folding pass.
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llvm-svn: 31065
2006-10-20 17:42:20 +00:00
0408e5b7ce
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
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llvm-svn: 31024
2006-10-17 22:41:45 +00:00
63007919dc
remove some dead code
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llvm-svn: 30938
2006-10-13 20:40:42 +00:00
d9e4bf5285
update comments
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llvm-svn: 30663
2006-09-28 23:33:12 +00:00
11b0a5dbd4
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
66ed41cac1
Can't commute shufps. The high / low parts elements come from different vectors.
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llvm-svn: 29275
2006-07-25 20:25:40 +00:00
c0f90bef47
Commute shufps / shufpd.
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llvm-svn: 28577
2006-05-30 23:34:30 +00:00
f21045a5cd
Somehow I lost a condition when I was shuffling some code around. Anyway,
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only transform a shufps to pshufd when the first two operands are the same.
llvm-svn: 28575
2006-05-30 22:13:36 +00:00
c8c172eaae
Fix a build breaker.
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llvm-svn: 28574
2006-05-30 21:45:53 +00:00
Evan Cheng