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18083 Commits

Author SHA1 Message Date
Evan Cheng 7511fa280d Reverting back to 1.723. The last two commits broke JM (and possibily others) on ARM. 
llvm-svn: 35620
 2007-04-03 08:11:50 +00:00
Evan Cheng e8315fe3f5 Inverted logic. 
llvm-svn: 35619
 2007-04-03 06:44:25 +00:00
Evan Cheng 06a7041ff9 Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found. 
llvm-svn: 35618
 2007-04-03 06:43:29 +00:00
Bill Wendling 652c7b2d73 Changed to new MMX_ recipes. 
llvm-svn: 35617
 2007-04-03 06:18:31 +00:00
Bill Wendling e7b2a864f2 Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. 
llvm-svn: 35616
 2007-04-03 06:00:37 +00:00
Chris Lattner 81e0707552 split some code out into a helper function 
llvm-svn: 35615
 2007-04-03 05:11:24 +00:00
Chris Lattner 64c764cebc Split a whole ton of code out of visitICmpInst into visitICmpInstWithInstAndIntCst. 
llvm-svn: 35614
 2007-04-03 04:46:52 +00:00
Chris Lattner 8b2ec5f506 Fix PR1253 and xor2.ll:test[01] 
llvm-svn: 35612
 2007-04-03 01:47:41 +00:00
Chris Lattner f742e2fe70 Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609
 2007-04-03 00:13:57 +00:00
Chris Lattner f3197a7d53 allow -1 strides to reuse "1" strides. 
llvm-svn: 35607
 2007-04-02 22:51:58 +00:00
Scott Michel 16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Dale Johannesen d13786dd82 fix off by 1 error in displacement computation 
llvm-svn: 35602
 2007-04-02 20:31:06 +00:00
Chris Lattner 8e168a4f36 fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.

llvm-svn: 35601
 2007-04-02 18:51:18 +00:00
Evan Cheng 476fb6a5c9 Ugh. Copy coalescer does not update register numbers. 
llvm-svn: 35600
 2007-04-02 18:49:18 +00:00
Chris Lattner 6223e83f6d add support for the 'w' inline asm register class. 
llvm-svn: 35598
 2007-04-02 17:24:08 +00:00
Zhou Sheng 9bc8ab100d 1. Make use of APInt operation instead of using ConstantExpr::getXXX. 
2. Use cheaper APInt methods.

llvm-svn: 35594
 2007-04-02 13:45:30 +00:00
Zhou Sheng 56cda95658 Use uint32_t for bitwidth instead of unsigned. 
llvm-svn: 35593
 2007-04-02 08:20:41 +00:00
Chris Lattner 28e0e4e11e Pass the type of the store access, not the type of the store, into the 
target hook.  This allows us to codegen a loop as:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0, +r3, lsl #2]
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

instead of:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0], #+4
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

This looks the same, but has one fewer induction variable (and therefore,
one fewer register) live in the loop.

llvm-svn: 35592
 2007-04-02 06:34:44 +00:00
Chris Lattner 3e21eb7fd7 Fix a bug which caused us to never be able to use signed comparisons for 
equality comparisons of a constant.  This allows us to codegen the 'sintzero'
loop in PR1288 as:

LBB1_1: ;cond_next
        li r4, 0
        addi r2, r2, 1
        stw r4, 0(r3)
        addi r3, r3, 4
        cmpwi cr0, r2, -1
        bne cr0, LBB1_1 ;cond_next

instead of:

LBB1_1: ;cond_next
        addi r2, r2, 1
        li r4, 0
        xoris r5, r2, 65535
        stw r4, 0(r3)
        addi r3, r3, 4
        cmplwi cr0, r5, 65535
        bne cr0, LBB1_1 ;cond_next

This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.

llvm-svn: 35590
 2007-04-02 05:59:42 +00:00
Chris Lattner 9d5aacee92 Wrap long line 
llvm-svn: 35588
 2007-04-02 05:48:58 +00:00
Chris Lattner 50490d54f2 use more obvious function name. 
llvm-svn: 35587
 2007-04-02 05:42:22 +00:00
Chris Lattner a3e0bb4ebb Treat xor of signbit like an add. 
llvm-svn: 35586
 2007-04-02 05:41:38 +00:00
Chris Lattner b24acc7bee simplify (x+c)^signbit as (x+c+signbit), pointed out by PR1288. This implements 
test/Transforms/InstCombine/xor.ll:test28

llvm-svn: 35584
 2007-04-02 05:36:22 +00:00
Chris Lattner b7b75145f1 reduce use of std::set 
llvm-svn: 35576
 2007-04-02 01:44:59 +00:00
Chris Lattner c3748562bd Various passes before isel split edges and do other CFG-restructuring changes. 
isel has its own particular features that it wants in the CFG, in order to
reduce the number of times a constant is computed, etc.  Make sure that we
clean up the CFG before doing any other things for isel.  Doing so can
dramatically reduce the number of split edges and reduce the number of
places that constants get computed.  For example, this shrinks
CodeGen/Generic/phi-immediate-factoring.ll from 44 to 37 instructions on X86,
and from 21 to 17 MBB's in the output.  This is primarily a code size win,
not a performance win.

This implements CodeGen/Generic/phi-immediate-factoring.ll and PR1296.

llvm-svn: 35575
 2007-04-02 01:35:34 +00:00
Lauro Ramos Venancio 6be85337b0 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Reid Spencer fad9bd6b92 For PR1297: 
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567
 2007-04-02 01:01:49 +00:00
Chris Lattner 8fe3cbe6bd print the type of an inserted IV in -debug mode. 
llvm-svn: 35563
 2007-04-01 22:21:39 +00:00
Chris Lattner c3eeb42809 simplify this code, make it work for ap ints 
llvm-svn: 35561
 2007-04-01 20:57:36 +00:00
Chris Lattner 59a6fa7af6 fix breakage from last night, simplify code. 
llvm-svn: 35560
 2007-04-01 20:49:36 +00:00
Reid Spencer add6123405 The bit counting intrinsics return i32 not the operand type. This fixes 
last night's regression in SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls

llvm-svn: 35556
 2007-04-01 18:42:20 +00:00
Zhou Sheng 150f3bbab2 Avoid unnecessary APInt construction. 
llvm-svn: 35555
 2007-04-01 17:13:37 +00:00
Evan Cheng 17d48a8bc2 Add i16 address mode. 
llvm-svn: 35551
 2007-04-01 08:06:46 +00:00
Reid Spencer 6bba6c8143 For PR1297: 
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547
 2007-04-01 07:35:23 +00:00
Reid Spencer 3a0843e734 For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
 2007-04-01 07:34:11 +00:00
Reid Spencer a090ffb2ab For PR1297: 
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
 2007-04-01 07:32:19 +00:00
Reid Spencer 2a2117c82d For PR1297: 
Implement "actual" argument types for the Intrinsic member functions. This
involves changing the getName, getType, and getDeclaration methods to have
optional parameters for the actual types. These are necessary in order for
the type/name to be constructed properly for overloaded intrinsics. Only
the caller knows the actual argument types desired.

llvm-svn: 35541
 2007-04-01 07:25:33 +00:00
Reid Spencer 7c57b88b27 For PR1297: 
1. Clear up confusion between "GotBits" and "ExpectBits". GotBits is the
   type actually provided. ExpectedBits is the type expected for the
   intrinsics. Before this patch, it was reversed!
2. Implement checks for overloaded intrinsics. This involves computing the
   suffix expected and making sure the suffix matches the function name. It
   also includes some intrinsic-specific checks such as ensuring that the
   bswap parameter and result are the same width and an even number of bytes.

llvm-svn: 35540
 2007-04-01 07:22:57 +00:00
Chris Lattner 0427799531 Fix InstCombine/2007-03-31-InfiniteLoop.ll 
llvm-svn: 35536
 2007-04-01 05:36:37 +00:00
Nick Lewycky f22938af1b Implement union of wrapped sets. 
llvm-svn: 35534
 2007-04-01 03:47:44 +00:00
Andrew Lenharth 427ec7fa51 Readme 
llvm-svn: 35533
 2007-03-31 15:05:44 +00:00
Anton Korobeynikov a8cc1ebae1 Consistency with native compilers 
llvm-svn: 35532
 2007-03-31 13:11:52 +00:00
Bill Wendling b72fcddd23 Fix comment. 
llvm-svn: 35531
 2007-03-31 09:36:12 +00:00
Chris Lattner 075b4db621 add a note 
llvm-svn: 35530
 2007-03-31 07:06:25 +00:00
Chris Lattner f6a6d3c8b0 move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
llvm-svn: 35529
 2007-03-31 04:18:03 +00:00
Chris Lattner f2836d17b6 Split the sdisel code munging stuff out into its own opt-pass, CodeGenPrepare. 
llvm-svn: 35528
 2007-03-31 04:06:36 +00:00
Chris Lattner f2d71d49e2 switch TL::getValueType to use MVT::getValueType. 
llvm-svn: 35527
 2007-03-31 04:05:24 +00:00
Chris Lattner 516f38b35f add a method to turn a type into a VT. 
llvm-svn: 35526
 2007-03-31 04:03:02 +00:00
Zhou Sheng 82c42284f4 Delete dead code. 
llvm-svn: 35525
 2007-03-31 02:50:26 +00:00
Zhou Sheng 4f16402e0d Use APInt operators to calculate the carry bits, remove this loop. 
llvm-svn: 35524
 2007-03-31 02:38:39 +00:00