llvm-project

Commit Graph

Author	SHA1	Message	Date
Tim Northover	58672974a9	ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations. This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048	2016-03-09 18:54:42 +00:00
Tim Northover	0f6c9d0a9b	ARM NEON: add vcvtX (with rounding mode) intrinsics to v8 ARM. These instructions (well, the f32 ones) are supported on 32-bit ARMv8, not just AArch64. Now that the arm_neon.td refactoring is complete, adding them is surprisingly simple. rdar://problem/16035743 llvm-svn: 201661	2014-02-19 10:37:13 +00:00

Author

SHA1

Message

Date

Tim Northover

58672974a9

ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.

This is mostly a one-time autoconversion of tests that checked assembly after
"-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This
should make them much more stable to changes in LLVM so they won't break on
unrelated changes.

"opt -mem2reg" is a compromise designed to increase the readability of tests
that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is
stable enough that no surpises will come along.

Should address http://llvm.org/PR26815.

llvm-svn: 263048

2016-03-09 18:54:42 +00:00

Tim Northover

0f6c9d0a9b

ARM NEON: add vcvtX (with rounding mode) intrinsics to v8 ARM.

These instructions (well, the f32 ones) are supported on 32-bit ARMv8, not just
AArch64. Now that the arm_neon.td refactoring is complete, adding them is
surprisingly simple.

rdar://problem/16035743

llvm-svn: 201661

2014-02-19 10:37:13 +00:00

2 Commits