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57 Commits

Author SHA1 Message Date
Michael Liao 95d9440348 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.

llvm-svn: 179266
 2013-04-11 04:52:28 +00:00
Kay Tiong Khoo 394bf1482b fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases 
llvm-svn: 179223
 2013-04-10 21:52:25 +00:00
Kevin Enderby f15856ebb4 Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048

llvm-svn: 176828
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo 7b564da474 death to extra whitespace 
llvm-svn: 175200
 2013-02-14 19:15:14 +00:00
Kay Tiong Khoo f809c6491d added basic support for Intel ADX instructions 
-feature flag, instructions definitions, test cases

llvm-svn: 175196
 2013-02-14 19:08:21 +00:00
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper 4eb9616b24 Add the tests that were supposed to go with r153935 that I forgot svn add 
llvm-svn: 154165
 2012-04-06 07:09:59 +00:00