Commit Graph

21545 Commits

Author SHA1 Message Date
Justin Holewinski 124e93de93 [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment of function parameters
llvm-svn: 194410
2013-11-11 19:28:19 +00:00
Justin Holewinski 4f5bc9b33a [NVPTX] Fix logic error in loading vector parameters of more than 4 components
llvm-svn: 194409
2013-11-11 19:28:16 +00:00
Chad Rosier d3684a0566 [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406
2013-11-11 19:11:11 +00:00
Chad Rosier 35575e737c [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194394
2013-11-11 18:04:07 +00:00
Daniel Sanders a1840d2f88 Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too
Reviewers: dsanders

Reviewed By: dsanders

CC: llvm-commits, nadav

Differential Revision: http://llvm-reviews.chandlerc.com/D1958

llvm-svn: 194393
2013-11-11 17:23:41 +00:00
Matheus Almeida c051a40506 [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.
No functional changes.

llvm-svn: 194391
2013-11-11 16:46:20 +00:00
Matheus Almeida ce207fa078 [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.
No functional changes.

llvm-svn: 194390
2013-11-11 16:38:55 +00:00
Matheus Almeida fed22ad33b [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.
No functional changes.

llvm-svn: 194389
2013-11-11 16:31:46 +00:00
Matheus Almeida c596839e67 [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.
No functional changes.

llvm-svn: 194387
2013-11-11 16:24:53 +00:00
Matheus Almeida 9826d07a2f [mips][msa] CHECK-DAG-ize MSA 2r.ll test.
No functional changes.

llvm-svn: 194386
2013-11-11 16:16:53 +00:00
Rafael Espindola 9d34018954 Add a testcase for pr17852.
llvm-svn: 194385
2013-11-11 15:37:52 +00:00
Hal Finkel c6a243987d Add PPC option for full register names in asm
On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

llvm-svn: 194384
2013-11-11 14:58:40 +00:00
Peter Zotov 18636a8777 [OCaml] Add missing Llvm_target functions
llvm-svn: 194382
2013-11-11 14:47:28 +00:00
Peter Zotov dfa957746c [OCaml] Accept context explicitly in Llvm_target functions
Llvm_target.intptr_type used to implicitly use global context. As
none of other functions in OCaml bindings do, it is changed to
accept context explicitly.

llvm-svn: 194381
2013-11-11 14:47:20 +00:00
Peter Zotov d52cf17584 [OCaml] Make Llvm_target.DataLayout.t automatically managed
This breaks the API by removing Llvm_target.DataLayout.dispose.

llvm-svn: 194380
2013-11-11 14:47:11 +00:00
Evgeniy Stepanov 560e089355 [msan] Propagate origin for insertvalue, extractvalue.
llvm-svn: 194374
2013-11-11 13:37:10 +00:00
NAKAMURA Takumi 5c0be2f67a Mark 36 tests as XFAIL:vg_leak in llvm/test/TableGen.
In historical reason, tblgen is not strictly required to be free from memory leaks.
For now, I mark them as XFAIL, they could be fixed, though.

llvm-svn: 194353
2013-11-10 14:26:08 +00:00
NAKAMURA Takumi cae86ce38b Remove 6 of XFAIL(s) in llvm/test/TableGen, since r193736. They have been XPASSing.
llvm-svn: 194352
2013-11-10 14:25:44 +00:00
Bill Wendling fed6c220ec Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus a fix to PR17307 & 17308."
This causes PR17852.

This reverts commit d93e8a06b2ca09ab18f390cd514b7443e2e571f7.

Conflicts:
	test/Transforms/GVN/cond_br2.ll

llvm-svn: 194348
2013-11-10 07:34:34 +00:00
Nadav Rotem 5ba1c6ced8 SimplifyCFG has a heuristics for out-of-order processors that decides when it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite.
llvm-svn: 194346
2013-11-10 04:13:31 +00:00
Matt Arsenault ba035bce21 Resolve TODO in test now that filecheck has multiple check prefixes.
llvm-svn: 194344
2013-11-10 02:16:47 +00:00
Matt Arsenault 13df462691 Allow multiple check prefixes in FileCheck.
This is useful if you want to run multiple variations
of a single test, and the majority of check lines
should be the same.

llvm-svn: 194343
2013-11-10 02:04:09 +00:00
Matt Arsenault 5bcefabcda Teach MergeFunctions about address spaces
llvm-svn: 194342
2013-11-10 01:44:37 +00:00
Matt Arsenault 0fb71e545c Use variable for register name in test
llvm-svn: 194338
2013-11-10 00:57:17 +00:00
Reed Kotler 45c5927c5c Mostly finish up constant islands port for Mips for load constants.
Still need to finish the branch part. Still lots more review of the code,
clean up and testing. 

llvm-svn: 194337
2013-11-10 00:09:26 +00:00
Akira Hatanaka d1c58ed8a7 [mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
 

llvm-svn: 194309
2013-11-09 02:38:51 +00:00
Juergen Ributzka 87ed906b2e [Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.

Differential Revision: http://llvm-reviews.chandlerc.com/D2074

Reviewed by Andy

llvm-svn: 194306
2013-11-09 01:51:33 +00:00
Juergen Ributzka 9969d3e6e8 [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.
The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

llvm-svn: 194293
2013-11-08 23:28:16 +00:00
Jim Grosbach 2fca51d3b4 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

llvm-svn: 194285
2013-11-08 22:33:06 +00:00
Quentin Colombet b06a0ed4b0 [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when setting
isPhysRegUsed if the unwind information is required.
Indeed, the runtime may need a correct stack to be able to unwind the call.

llvm-svn: 194271
2013-11-08 18:14:17 +00:00
Tim Northover 93bcc66e73 ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
    push {r7, lr}
    sub sp, sp, #4

If code size is extremely important, this can be optimised to the single
instruction:
    push {r6, r7, lr}

where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.

This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.

llvm-svn: 194264
2013-11-08 17:18:07 +00:00
Artyom Skrobov 202ff08f97 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
llvm-svn: 194263
2013-11-08 16:25:50 +00:00
Artyom Skrobov d2116a4ef7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194262
2013-11-08 16:17:14 +00:00
Artyom Skrobov e686cec7d4 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194261
2013-11-08 16:16:30 +00:00
Zoran Jovanovic 2914d2d980 Test for microMIPS trap instructions.
llvm-svn: 194258
2013-11-08 14:55:31 +00:00
NAKAMURA Takumi 0d82bac470 llvm-ar: Let opening a directory failed in llvm-ar.
Linux cannot open directories with open(2), although cygwin and *bsd can.

Motivation: The test, Object/directory.ll, had been failing with --target=cygwin on Linux. XFAIL was improper for host issues.
llvm-svn: 194257
2013-11-08 12:35:56 +00:00
Matheus Almeida a3bac16950 [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.

llvm-svn: 194255
2013-11-08 10:43:11 +00:00
Artyom Skrobov 8653443902 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
llvm-svn: 194253
2013-11-08 09:16:31 +00:00
David Majnemer bd4fef4a89 IR: Do not canonicalize constant GEPs into an out-of-bounds array access
Summary:
Consider a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 0)

If we proceeded to GEP the aforementioned object by 8, would form a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 8)

Note that we would go through the first array member, causing an
out-of-bounds accesses.  This is problematic because we might get fooled
if we are trying to evaluate loads using this GEP, for example, based
off of an object with a constant initializer where the array is zero.

This fixes PR17732.

Reviewers: nicholas, chandlerc, void

Reviewed By: void

CC: llvm-commits, echristo, void, aemerson

Differential Revision: http://llvm-reviews.chandlerc.com/D2093

llvm-svn: 194220
2013-11-07 22:15:53 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1.
llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Vincent Lejeune 4f3751f2af R600: Fix LowerUDIVREM
llvm-svn: 194153
2013-11-06 17:36:04 +00:00
Benjamin Kramer 9e9773d46d Add test case for PR12377, it was fixed by r194116.
llvm-svn: 194147
2013-11-06 11:55:41 +00:00
Vladimir Medic 4c29985cd0 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
llvm-svn: 194145
2013-11-06 11:27:05 +00:00
Peter Zotov 578267fb73 [OCaml] Impement Llvm_irreader, bindings to LLVM assembly parser
llvm-svn: 194138
2013-11-06 09:21:25 +00:00
Peter Zotov d10ae6c527 [OCaml] Implement Llvm.string_of_llvalue
llvm-svn: 194136
2013-11-06 09:21:08 +00:00
Jiangning Liu f4226f1d7b Implement AArch64 Neon instruction set Perm.
llvm-svn: 194123
2013-11-06 03:35:27 +00:00
Jiangning Liu a50e22ca4f Implement AArch64 Neon instruction set Bitwise Extract.
llvm-svn: 194118
2013-11-06 02:25:49 +00:00
Andrew Trick 34e2f0c4ea Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

llvm-svn: 194116
2013-11-06 02:08:26 +00:00
Andrew Trick 6664df12fb Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

llvm-svn: 194102
2013-11-05 22:44:04 +00:00
Tim Northover f02287db27 ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094
2013-11-05 21:36:02 +00:00