llvm-project

Commit Graph

Author	SHA1	Message	Date
Ehsan Amiri	a538b0f023	Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624	2016-08-03 18:17:35 +00:00
Ahmed Bougacha	082c5c707a	Add a bunch of CHECK missing colons in tests. NFC. Some wouldn't pass; fixed most, the rest will be fixed separately. llvm-svn: 232239	2015-03-14 01:43:57 +00:00
Kit Barton	0cfa7b7ad0	Add the following 64-bit vector integer arithmetic instructions added in POWER8: vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115	2015-03-03 19:55:45 +00:00

Author

SHA1

Message

Date

Ehsan Amiri

a538b0f023

Adding -verify-machineinstrs option to PowerPC tests

Currently we have a number of tests that fail with -verify-machineinstrs.
To detect this cases earlier we add the option to the testcases with the
exception of tests that will currently fail with this option. PR 27456 keeps
track of this failures.

No code review, as discussed with Hal Finkel.

llvm-svn: 277624

2016-08-03 18:17:35 +00:00

Ahmed Bougacha

082c5c707a

Add a bunch of CHECK missing colons in tests. NFC.

Some wouldn't pass;  fixed most, the rest will be fixed separately.

llvm-svn: 232239

2015-03-14 01:43:57 +00:00

Kit Barton

0cfa7b7ad0

Add the following 64-bit vector integer arithmetic instructions added in POWER8:

vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959

llvm-svn: 231115

2015-03-03 19:55:45 +00:00

3 Commits