b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
5800a8c3ad
Cast through intptr_t, ISO C++ requires it.
...
llvm-svn: 138186
2011-08-20 02:22:42 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
...
llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
...
llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
...
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
...
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
...
needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
8022015a16
Fix NEG alias
...
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
066e9ec1e4
Update tests.
...
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
...
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
9c92049069
Tab characters.
...
llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
...
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
...
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
...
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
...
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
...
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
...
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
...
llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
...
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
...
llvm-svn: 138042
2011-08-19 16:52:32 +00:00
024d2614b6
Have SPU backend use the external TCE scheduler, if the library is loaded as a
...
module.
Patch by Pekka Jääskeläinen.
llvm-svn: 138037
2011-08-19 10:50:24 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
llvm-svn: 138034
2011-08-19 05:28:50 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
4938edb02c
Make a bunch of symbols private.
...
llvm-svn: 138025
2011-08-19 01:42:18 +00:00
5647d84aa4
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
...
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
llvm-svn: 138012
2011-08-18 23:59:21 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
...
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
...
anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
...
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
...
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
...
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
...
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
...
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
6ddb568ab8
Add missing 'break'.
...
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
...
llvm-svn: 137938
2011-08-18 13:00:48 +00:00
3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
...
v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
...
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
...
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
...
shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
d14b70d00b
Tidy up. 80 columns.
...
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
...
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
854fe433d4
Fix predicate for imm1_32
...
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
3b5a69cc45
80 columns.
...
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
...
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
...
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
...
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
...
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
6d33c7f303
Update comments about vector splat handling in x86
...
llvm-svn: 137808
2011-08-17 02:29:13 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
...
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
...
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
...
llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
...
llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
...
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
77f1fd5e44
Define function MipsMCInstLower::LowerOperand.
...
llvm-svn: 137707
2011-08-16 02:21:03 +00:00
6520b9857f
Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.
...
llvm-svn: 137706
2011-08-16 02:15:03 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
...
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
c1676e41c0
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
...
also add the AVX versions of the 128-bit patterns
llvm-svn: 137685
2011-08-15 23:36:51 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
...
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
...
when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
...
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
...
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
...
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
c53dd2ac01
Fix comment!
...
llvm-svn: 137521
2011-08-12 21:54:42 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
...
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
960c8f71aa
Move code around and add comments
...
llvm-svn: 137518
2011-08-12 21:48:22 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
...
Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
...
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
...
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
...
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
7bd6e6ebef
When constant double 0.0 is lowered, make sure 0 is copied directly from an
...
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
llvm-svn: 137484
2011-08-12 18:09:59 +00:00
01becebef3
switch to the new struct apis.
...
llvm-svn: 137481
2011-08-12 18:07:07 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
...
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
...
when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
210bf8351d
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
...
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
llvm-svn: 137404
2011-08-12 00:49:19 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
...
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
...
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
...
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
...
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
...
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
...
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
...
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
88981ff168
Tidy up comment.
...
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
...
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
6d8c039ab1
Add isIndirectBranch flag.
...
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
2ea19d1438
Tidy up. Remove unused template parameter.
...
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
1b0f79573e
Tidy up.
...
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
043c820800
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
...
llvm-svn: 137324
2011-08-11 18:59:13 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
efdd183f52
Add a comment, per Bruno's CR.
...
llvm-svn: 137313
2011-08-11 17:05:47 +00:00
1542d5a00a
[AVX] If the data which is going to be saved is already in two XMM registers
...
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
llvm-svn: 137308
2011-08-11 16:41:21 +00:00
dbd1352c80
Cleanup: Remove Int_ CVTSS2SI* forms
...
llvm-svn: 137297
2011-08-11 02:52:36 +00:00
a2d8bb97b9
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
...
infinite recursive calls in legalize. Fix PR10562
llvm-svn: 137296
2011-08-11 02:49:44 +00:00
572c9aaf53
Use the splat index to generate the desired shuffle. Otherwise we
...
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
llvm-svn: 137295
2011-08-11 02:49:41 +00:00
3ae39f8ad1
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
...
Fixes PR9693.
llvm-svn: 137292
2011-08-11 01:48:05 +00:00
d5d6359785
ARM LDRT assembly parsing and encoding.
...
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
d3f7bcd43c
Tidy up. 80 columns.
...
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
f7164b2cfd
Fix typo. Not quite sure how that slipped in there.
...
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
410a11fe82
When performing a truncating store, it is sometimes possible to rearrange the
...
data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
llvm-svn: 137238
2011-08-10 19:30:14 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
3ff111c12d
The following X86 pattern is incorrect:
...
def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
llvm-svn: 137227
2011-08-10 17:45:17 +00:00
1531e5cd2b
Tabs --> spaces.
...
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
5d69f63bbb
Cleanups based on Nick Lewycky's feedback.
...
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
732f82c463
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
...
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
36a3abc671
Add support for the R and Q constraints.
...
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
278ffd7d8e
Fix a bug in vpermilps mask checking. Fix PR10560
...
llvm-svn: 137194
2011-08-10 01:54:17 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
6a14dc01ff
Promote VMOVS to VMOVD when possible.
...
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
llvm-svn: 137182
2011-08-09 23:41:44 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
72323966c8
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
...
llvm-svn: 137179
2011-08-09 23:27:13 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
fc481959d2
Add v16i16 and v32i8 store patterns
...
llvm-svn: 137166
2011-08-09 22:39:53 +00:00
6963062a99
Use fp unpack instructions to unpack int types. Until we have AVX2, this
...
is the best we can do for these patterns. This fix PR10554.
llvm-svn: 137161
2011-08-09 22:18:37 +00:00
4ef2426b87
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
...
llvm-svn: 137160
2011-08-09 22:17:39 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
d151b09921
Silence an false-positive warning.
...
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
d770f6c110
Don't generate the old-style disassembler in CMake builds either.
...
llvm-svn: 137153
2011-08-09 21:36:11 +00:00
de2c381331
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
...
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
982aa05017
Don't continue generating the old-style decoder file.
...
llvm-svn: 137150
2011-08-09 21:30:29 +00:00
5e80abbb5d
ARM fix typo in pre-indexed store lowering.
...
rdar://9915869
llvm-svn: 137148
2011-08-09 21:22:41 +00:00
c7afd84322
Attempt to fix CMake build.
...
llvm-svn: 137147
2011-08-09 21:09:59 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
d7f41b7f66
Revert r137134. It breaks some code as Eli pointed out.
...
llvm-svn: 137135
2011-08-09 18:56:35 +00:00
84ec8f65d1
Print out the variable declaration only if it is a declaration. Otherwise, a
...
'static' variable will be emitted twice.
PR10081
llvm-svn: 137134
2011-08-09 18:31:50 +00:00
bed48dc8ff
Reapply a more appropriate solution than in r137114. AVX supports
...
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.
llvm-svn: 137128
2011-08-09 17:39:13 +00:00
24dd1d4a27
Revert r137114
...
llvm-svn: 137127
2011-08-09 17:39:01 +00:00
db05c2b963
PTX: Add initial support for device function calls
...
- Calls are supported on SM 2.0+ for function with no return values
llvm-svn: 137125
2011-08-09 17:36:31 +00:00
faff512536
Emitting ARM build attributes and values as ULEB, rather than char.
...
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
ad3453cf2d
Handle sitofp between v4f64 <- v4i32. Fix PR10559
...
llvm-svn: 137114
2011-08-09 05:48:01 +00:00
1155b1eafa
Add support for avx vector fextend
...
llvm-svn: 137105
2011-08-09 03:04:29 +00:00
0d0964d099
Add AVX versions of 128-bit sitofp and fptosi
...
llvm-svn: 137104
2011-08-09 03:04:25 +00:00
2fc107365b
Add two patterns to match special vmovss and vmovsd cases. Also fix
...
the patterns already there to be more strict regarding the predicate.
This fixes PR10558
llvm-svn: 137100
2011-08-09 01:43:09 +00:00
413bff1b3b
Add missing attributes to the C++ backend's output.
...
llvm-svn: 137091
2011-08-09 00:47:30 +00:00
af6a85484c
Make LowerVSETCC aware of AVX types and add patterns to match them.
...
llvm-svn: 137090
2011-08-09 00:46:57 +00:00
cab35c0836
ARM parsing and encoding for LDRBT instruction.
...
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
03ac20fc66
Thumb1 BL instructions encoding 22 bits of displacement, not 21.
...
llvm-svn: 137073
2011-08-08 23:25:22 +00:00
c04a66b48e
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
...
They improve the verbose assembly.
llvm-svn: 137069
2011-08-08 21:45:32 +00:00
c96953c12a
Add support for several vector shifts operations while in AVX mode. Fix PR10581
...
llvm-svn: 137067
2011-08-08 21:31:08 +00:00
95466ce63b
ARM load/store label parsing.
...
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
llvm-svn: 137064
2011-08-08 20:59:31 +00:00
daa2cad723
Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
...
These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.
llvm-svn: 137063
2011-08-08 20:53:24 +00:00
c40303885b
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
...
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
a27da98921
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
...
llvm-svn: 137061
2011-08-08 19:49:37 +00:00
c22d50e5c3
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
...
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
llvm-svn: 137059
2011-08-08 18:56:44 +00:00
4f0ace5674
Don't clobber pending ST regs when FP regs are killed.
...
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints. It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.
When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.
This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.
This fixes PR10602.
llvm-svn: 137050
2011-08-08 17:15:43 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
...
Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
c320c85261
ARM indexed load assembly parsing and encoding.
...
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
f0c95cadc7
ARM refactor indexed store instructions.
...
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
llvm-svn: 136978
2011-08-05 20:35:44 +00:00
a70fbfd577
ARM simplify the postidx_reg operand encoding.
...
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
llvm-svn: 136969
2011-08-05 16:11:38 +00:00
bafce840ff
ARM use a dedicated printer for postidx_reg operands.
...
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
8de11bab76
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
...
<rdar://problem/9878189>
llvm-svn: 136962
2011-08-05 07:24:09 +00:00
2536b51aae
Silence unused variable warnings in release builds.
...
llvm-svn: 136956
2011-08-05 01:08:21 +00:00
239370cb3f
Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte fixups to be added
...
llvm-svn: 136954
2011-08-05 00:53:03 +00:00
08d4bb0f12
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
...
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
cd17c12078
ARM assembly parsing and encoding for LDR instructions.
...
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.
llvm-svn: 136940
2011-08-04 23:01:30 +00:00
19e3f80579
Fix an obvious type. Patch by Ivan Krasin.
...
llvm-svn: 136899
2011-08-04 18:38:15 +00:00
ce5190321e
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
...
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
00f39c1521
Add obviously missing "break". Noticed by Andrey Karpov with
...
the PVS-studio tool.
llvm-svn: 136878
2011-08-04 15:45:59 +00:00
e4df09f7ba
Fix http://llvm.org/bugs/show_bug.cgi?id=10568
...
Move the reloc size assert into AsmBackend - where it is more apropos.
llvm-svn: 136855
2011-08-04 00:38:45 +00:00
e234f6ae0c
Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.
...
Fixes PR10527.
llvm-svn: 136853
2011-08-04 00:32:58 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
7bc3b11a56
Fix broken encoding of tCBNZ.
...
llvm-svn: 136837
2011-08-03 23:21:48 +00:00
30a49e93e3
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
...
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
llvm-svn: 136813
2011-08-03 21:06:02 +00:00
103e2ec2df
Remove unused variables.
...
llvm-svn: 136803
2011-08-03 19:53:48 +00:00
da618420ee
Handle IMPLICIT_DEF instructions in X86FloatingPoint.
...
This fixes PR10575.
llvm-svn: 136787
2011-08-03 16:33:19 +00:00
5c863aeefd
ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
...
llvm-svn: 136737
2011-08-02 22:44:16 +00:00
04c5025cd5
Don't create a ridiculous EXTRACT_ELEMENT. PR10563.
...
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.
llvm-svn: 136711
2011-08-02 18:38:35 +00:00
713406f88d
Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
...
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
c8c63914c5
Tidy up. 80 columns.
...
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
9ec152b6bf
ARM: rename addrmode7 to addr_offset_none.
...
Use a more descriptive name so the code is more self-documenting.
llvm-svn: 136704
2011-08-02 18:07:32 +00:00
5ada908140
Make this kind of lowering to be supported by 256-bit instructions:
...
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494
llvm-svn: 136691
2011-08-02 16:06:18 +00:00
e6a11dcc72
Remove trailing semicolon.
...
llvm-svn: 136690
2011-08-02 15:54:03 +00:00
038c1a1a73
Sketch out PowerPC ELF writer. This is enough to get clang -integrated-as
...
to compile a working hello world on FreeBSD/PPC32.
llvm-svn: 136689
2011-08-02 15:51:38 +00:00
a530a4d925
Bail from FastISel when we encounter a volatile memset intrinsic. Patch by Ivan
...
Krasin!
llvm-svn: 136663
2011-08-02 00:40:16 +00:00
9f620a6883
Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
...
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
0f731b3232
Fix comments.
...
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
a8e3673816
Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
...
the legalizer. This commit together with the two previous ones fixes
PR10495.
llvm-svn: 136654
2011-08-01 21:54:09 +00:00
616fe60548
Teach PreprocessISelDAG to be aware of vector types and to not process them.
...
llvm-svn: 136653
2011-08-01 21:54:05 +00:00
bd30a4b584
Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead of
...
using a stack store.
llvm-svn: 136652
2011-08-01 21:54:02 +00:00
c099a6f9ce
Actually finish switching to the new system for Target sublibrary
...
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.
This should fix some of the random race-condition failures people are
still seeing with CMake.
llvm-svn: 136643
2011-08-01 19:55:11 +00:00
7513939ddd
Since vectors with all ones can't be created with a 256-bit instruction,
...
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547
llvm-svn: 136642
2011-08-01 19:51:53 +00:00
de4ae46607
Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky.
...
llvm-svn: 136639
2011-08-01 19:43:05 +00:00
0cc000ef29
Fix crash with varargs function with no named parameters.
...
llvm-svn: 136623
2011-08-01 16:45:59 +00:00
d41f3a161f
Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
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llvm-svn: 136621
2011-08-01 16:29:27 +00:00
f891bf8b30
Add the 'resume' instruction for the new EH rewrite.
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This adds the 'resume' instruction class, IR parsing, and bitcode reading and
writing. The 'resume' instruction resumes propagation of an existing (in-flight)
exception whose unwinding was interrupted with a 'landingpad' instruction (to be
added later).
llvm-svn: 136589
2011-07-31 06:30:59 +00:00
27246dc784
Switch another of the old dependencies on implicitly produced synthetic
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rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.
llvm-svn: 136567
2011-07-30 10:10:23 +00:00
ad088e6724
Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
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r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.
llvm-svn: 136556
2011-07-30 05:42:50 +00:00
aa5030066f
Add support for the 'Q' constraint.
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Fixes rdar://9866494
llvm-svn: 136523
2011-07-29 21:18:58 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
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Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
e537438ca5
ARM CPS mode immediate is 5 bits, not 4.
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llvm-svn: 136505
2011-07-29 20:02:39 +00:00
c4dc52cd52
ARM assembly parsing and encoding for RFE instruction.
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Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
20d38124a2
ARM SRS and RFE instructions are not code-gen only.
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llvm-svn: 136475
2011-07-29 17:51:39 +00:00
3b764cfd48
ARM range checking for mode on CPS instruction.
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llvm-svn: 136473
2011-07-29 17:42:17 +00:00
e658f4faeb
Update FIXME.
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llvm-svn: 136470
2011-07-29 17:36:04 +00:00
47859c8ab0
Tweak comment.
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llvm-svn: 136468
2011-07-29 17:33:29 +00:00
adec587d5c
Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
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working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)
llvm-svn: 136457
2011-07-29 03:05:32 +00:00
65ce5ea3ba
Fix two tests that I crashed in the previous commits. The mask elts
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on the second half must be reindexed.
llvm-svn: 136454
2011-07-29 02:05:28 +00:00
81eb193f2e
Match VPERMIL masks more strictly and update the target specific mask
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generation to always catch the weird cases.
llvm-svn: 136453
2011-07-29 01:31:15 +00:00
795f558532
Add DecodeShuffle shuffle support for VPERMIPD variantes
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llvm-svn: 136452
2011-07-29 01:31:11 +00:00
Owen Anderson