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18924 Commits

Author SHA1 Message Date
Evan Cheng 0b758ed6ba Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
 2011-09-06 18:52:20 +00:00
Jim Grosbach f471ac3c72 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155
 2011-09-06 18:46:23 +00:00
Rafael Espindola db5823dc77 Fix style issues and typos found by Duncan. 
llvm-svn: 139154
 2011-09-06 18:43:08 +00:00
Jakob Stoklund Olesen 50ef7611aa Atomic pseudos don't use (as in read) CPSR. They clobber it. 
llvm-svn: 139148
 2011-09-06 17:40:35 +00:00
Duncan Sands a098436b32 Split the init.trampoline intrinsic, which currently combines GCC's 
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
 2011-09-06 13:37:06 +00:00
Nick Lewycky 73df7e3830 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
 2011-09-05 21:51:43 +00:00
Nick Lewycky df06b6e069 Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger! 
llvm-svn: 139124
 2011-09-05 18:50:59 +00:00
Nick Lewycky f1a5f57d2f Fix typo in comment. 
llvm-svn: 139122
 2011-09-05 18:35:03 +00:00
Benjamin Kramer 7859d2e148 Use internal storage for command line option. 
llvm-svn: 139079
 2011-09-03 03:45:06 +00:00
Bruno Cardoso Lopes 07d9914620 Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends 
the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073
 2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes 1d5c2d9227 Add AVX version of a SSE4.1 VPBLENDVB pattern 
llvm-svn: 139072
 2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes 212a8c4357 Add AVX versions of SSE4.1 EXTRACTPS patterns 
llvm-svn: 139071
 2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes 3d581a36b6 Add AVX versions for SSE4.1 MOVZX* patterns 
llvm-svn: 139070
 2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes 6d701fcef0 Add one more AVX pattern for MOVZPQILo2PQI 
llvm-svn: 139069
 2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes 9923c51564 Move PUNPCKLQDQ splat pattern close to the instruction definition and 
duplicate it for AVX mode.

llvm-svn: 139068
 2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes 96b11f39e2 Add AVX pattern versions for PSHUFB,PSIGN{B,W,D} 
llvm-svn: 139067
 2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes 9a0da1e57a Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate 
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066
 2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes 903952223a Enforce subtarget checks in a few places to be explicit when the 
pattern should be matched

llvm-svn: 139065
 2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes 521b0cfdc6 Tidy up code moving patterns to their appropriate place! 
llvm-svn: 139064
 2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes aad5e50ded Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use 
it!

llvm-svn: 139063
 2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes d893fc92af Teach X86FastISel to use AVX versions of instructions when possible 
llvm-svn: 139062
 2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes 006c9371a1 Fix 80-column and style 
llvm-svn: 139061
 2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes dbb40015ff Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of 
OptForSize pattern

llvm-svn: 139060
 2011-09-03 00:46:38 +00:00
Jakob Stoklund Olesen 1f72dd40c7 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen f08354d183 Check for EFLAGS live-out before clobbering it. 
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056
 2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen d0c8a31c8b Use existing function. 
llvm-svn: 139055
 2011-09-02 23:52:49 +00:00
Jim Grosbach 34842ceb97 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jakob Stoklund Olesen 38019e3188 Remove unused variables. 
llvm-svn: 139047
 2011-09-02 22:41:25 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach a216debb37 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Kevin Enderby 5b03f72292 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach 05dec8b122 Tidy up. Formatting. 
llvm-svn: 139024
 2011-09-02 18:46:15 +00:00
Jim Grosbach 0a57375a28 Tidy up. 80 columns. 
llvm-svn: 139022
 2011-09-02 18:43:25 +00:00
Jim Grosbach 370e923434 Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Bill Wendling 4e1d018935 Revert r138826 until PR10834 can be fixed. 
llvm-svn: 139018
 2011-09-02 18:15:04 +00:00
Jim Grosbach 2761155203 Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Kalle Raiskila f5769c1070 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 
llvm-svn: 139004
 2011-09-02 10:05:01 +00:00
Owen Anderson ed96b58bd2 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson 03aadae01f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman d7776ed030 Null-initialize to shut up -Wuninitialized warnings. 
llvm-svn: 138974
 2011-09-01 22:27:41 +00:00
Jim Grosbach f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes f61d1c072e Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
James Molloy db4ce60328 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson 35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Chad Rosier 17847ae757 Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach e1995f2566 Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Owen Anderson 4af0aa98d5 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00