cf7be39e24
dbg_value may end a block.
...
llvm-svn: 99378
2010-03-24 01:50:28 +00:00
aa9b1c81a7
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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llvm-svn: 99376
2010-03-24 01:29:25 +00:00
9096bcdeda
Switch INC8r to defining its pattern in terms of X86inc_flag
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and defining the add pattern with Pat<>, eliminating a use of
parallel.
llvm-svn: 99375
2010-03-24 01:02:12 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
b92c8c849b
Remove the ConvertActions table and associated code, which is unused.
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llvm-svn: 99372
2010-03-24 00:53:38 +00:00
f9c8bec6c5
switch SDTBinaryArithWithFlags to be a multiple-result node as well.
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llvm-svn: 99370
2010-03-24 00:49:29 +00:00
db1ac3cf3e
Switch SDTUnaryArithWithFlags to being modeled as a two-result
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ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
llvm-svn: 99369
2010-03-24 00:47:47 +00:00
cca83a7aa4
remove 64-bit or_is_add parallels.
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llvm-svn: 99360
2010-03-24 00:16:52 +00:00
f5e5004327
remove useless or_is_add parallel's.
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llvm-svn: 99359
2010-03-24 00:15:23 +00:00
237d38e748
reduce nesting.
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llvm-svn: 99358
2010-03-24 00:12:57 +00:00
e0874fa02f
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
llvm-svn: 99355
2010-03-24 00:03:13 +00:00
a86ccbfe88
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."
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This reverts commit 99345. It was breaking buildbots.
llvm-svn: 99352
2010-03-23 23:48:51 +00:00
5376c2a431
MC: Sprinkle in some more interesting statistics.
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llvm-svn: 99350
2010-03-23 23:47:14 +00:00
5cfb58719d
llvm-mc: Fast path EvaluateAbsolute of constants.
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llvm-svn: 99348
2010-03-23 23:47:07 +00:00
3d9ec39116
[llvm_void_ty] is no longer needed for result types,
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just use an empty result list.
llvm-svn: 99346
2010-03-23 23:46:07 +00:00
31da45b7af
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
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This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
llvm-svn: 99345
2010-03-23 23:14:44 +00:00
6a64320da8
Renamed NVdImmFrm to N1RegModImmFrm.
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llvm-svn: 99344
2010-03-23 23:09:14 +00:00
00eeac4179
add some accessors to callsite/callinst/invokeinst to check
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for the noinline attribute, and make the inliner refuse to
inline a call site when the call site is marked noinline even
if the callee isn't. This fixes PR6682.
llvm-svn: 99341
2010-03-23 22:59:07 +00:00
c53d5d6bb4
Revert 99335. getTypeToExpandTo's iterative behavior is actually
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needed here.
llvm-svn: 99339
2010-03-23 22:44:42 +00:00
42f8ddeb11
Remove getTypeToExpandTo, since it isn't adding much value
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beyond just calling getTypeToTransformTo.
llvm-svn: 99335
2010-03-23 22:15:31 +00:00
dcddd5701c
Don't back past debug info intrinsics; SCEVExpander's strategy
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for ignoring debug info intrinsics everywhere else is to advance
past them, and it needs to be consistent.
llvm-svn: 99332
2010-03-23 21:53:22 +00:00
ae12e35004
fix an infinite loop in Module::getEndianness, PR6684
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patch by Alex Mac!
llvm-svn: 99330
2010-03-23 21:48:41 +00:00
8a687233e3
Fix typo in the comment for N3VX class.
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llvm-svn: 99328
2010-03-23 21:35:03 +00:00
5be6d5a6a9
Add comment.
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llvm-svn: 99327
2010-03-23 21:30:12 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
04803e8ef6
Skip debugging intrinsics when sinking unused invariants.
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llvm-svn: 99324
2010-03-23 21:15:59 +00:00
020023a3fa
Add New NEON Format NVdVmImmFrm.
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llvm-svn: 99322
2010-03-23 20:40:44 +00:00
77be42a07f
Ignore dbg_value's.
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llvm-svn: 99321
2010-03-23 20:36:12 +00:00
b6dee6e015
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?
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llvm-svn: 99320
2010-03-23 20:35:45 +00:00
c7d721aa03
Code clean up.
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llvm-svn: 99319
2010-03-23 20:33:48 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
3968c6a252
Fix bad indentation, 80-column violations, and trailing whitespace.
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llvm-svn: 99295
2010-03-23 17:23:59 +00:00
ac5024bbeb
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
llvm-svn: 99288
2010-03-23 16:43:47 +00:00
d9e822345c
Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.
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llvm-svn: 99282
2010-03-23 15:48:04 +00:00
161cb044f3
add assert in argpromotion, which cannot trigger
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if Function::hasAddressTaken works as advertised
also included some cosmetic cleanups
llvm-svn: 99276
2010-03-23 14:40:20 +00:00
668d700fe3
word-o
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llvm-svn: 99275
2010-03-23 13:45:54 +00:00
9b680e21c0
Rename some instructions to match the corresponding NEON opcode.
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llvm-svn: 99266
2010-03-23 06:26:18 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
3f7842232e
Fix an incorrect logic causing instcombine to miss some _chk -> non-chk transformations.
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llvm-svn: 99263
2010-03-23 06:06:09 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
de04b3f62c
MC: Switch to using MCInst fragments to do relaxation.
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Also, both MCMachOStreamer and MCAssembler are now target independent!
llvm-svn: 99256
2010-03-23 05:09:03 +00:00
86face8333
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.
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llvm-svn: 99249
2010-03-23 03:13:05 +00:00
a9ae3ae698
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.
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llvm-svn: 99248
2010-03-23 02:36:58 +00:00
e0c43577c1
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.
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llvm-svn: 99245
2010-03-23 01:39:09 +00:00
16cbe95dd6
MC: Tweak MCInstFragment to include the encoded data and fixups, so that we don't need to recompute them during relaxation. I will revisit this once all the other pieces of fast relaxation are in place.
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llvm-svn: 99244
2010-03-23 01:39:05 +00:00
a99d232803
Put MCSectionCOFF::Name into the MCContext instead of leaking it.
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llvm-svn: 99231
2010-03-22 23:26:12 +00:00
b31c49a70d
MC: Add MCInstFragment, not used yet.
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llvm-svn: 99229
2010-03-22 23:16:48 +00:00
a75f01a905
Add a FIXME.
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llvm-svn: 99228
2010-03-22 23:16:43 +00:00
b1c4f62cac
Fix PR6673: updating the callback should not clear the map.
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llvm-svn: 99227
2010-03-22 23:15:57 +00:00
d22ed622b3
Emit DW_AT_low_pc and DW_AT_high_pc attributes for TAG_compile_unit.
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llvm-svn: 99225
2010-03-22 23:11:36 +00:00
Evan Cheng