Commit Graph

16742 Commits

Author SHA1 Message Date
Nicolai Haehnle 3b572002a2 AMDGPU: add execfix flag to SI_ELSE
Summary:
SI_ELSE is lowered into two parts:

s_or_saveexec_b64 dst, src (at the start of the basic block)

s_xor_b64 exec, exec, dst (at the end of the basic block)

The idea is that dst contains the exec mask of the preceding IF block. It can
happen that SIWholeQuadMode decides to switch from WQM to Exact mode inside
the basic block that contains SI_ELSE, in which case it introduces an instruction

s_and_b64 exec, exec, s[...]

which masks out bits that can correspond to both the IF and the ELSE paths.
So the resulting sequence must be:

s_or_savexec_b64 dst, src

s_and_b64 exec, exec, s[...] <-- added by SIWholeQuadMode
s_and_b64 dst, dst, exec <-- added by SILowerControlFlow

s_xor_b64 exec, exec, dst

Whether to add the additional s_and_b64 dst, dst, exec is currently determined
via the ExecModified tracking. With this change, it is instead determined by
an additional flag on SI_ELSE which is set by SIWholeQuadMode.

Finally: It also occured to me that an alternative approach for the long run
is for SILowerControlFlow to unconditionally emit

s_or_saveexec_b64 dst, src

...

s_and_b64 dst, dst, exec
s_xor_b64 exec, exec, dst

and have a pass that detects and cleans up the "redundant AND with exec"
pattern where possible. This could be useful anyway, because we also add
instructions

s_and_b64 vcc, exec, vcc

before s_cbranch_scc (in moveToALU), and those are often redundant. I have
some pending changes to how KILL is lowered that could also benefit from
such a cleanup pass.

In any case, this current patch could help in the short term with the whole
ExecModified business.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22846

llvm-svn: 276972
2016-07-28 11:39:24 +00:00
Krzysztof Parzyszek 06a2b6b1ee [Hexagon] Find speculative loop preheader in hardware loop generation
Before adding a new preheader block, check if there is a candidate block
where the loop setup could be placed speculatively. This will be off by
default.

llvm-svn: 276919
2016-07-27 21:20:54 +00:00
Krzysztof Parzyszek 5241b8efcf [Hexagon] Do not optimize volatile stack spill slots
llvm-svn: 276916
2016-07-27 20:50:42 +00:00
Andrew Kaylor 9155354ff2 Revert EH-specific checks in BranchFolding that were causing blow ups in compile time.
Differential Revision: https://reviews.llvm.org/D22839

llvm-svn: 276898
2016-07-27 17:55:33 +00:00
Tim Northover 8d2f52e035 GlobalISel: support zero-sized allocas
All allocas must be at least 1 byte at the MachineIR level so we allocate just
one byte.

llvm-svn: 276897
2016-07-27 17:47:54 +00:00
Simon Pilgrim 7efafbc583 [X86][SSE] Updated test so that both are applying the post-multiply
This is to ensure that there are no diffs other than due to buildvector/legalization

llvm-svn: 276882
2016-07-27 15:30:20 +00:00
Ahmed Bougacha 6756a2c953 [GlobalISel] Introduce an instruction selector.
And implement it for AArch64, supporting x/w ADD/OR.

Differential Revision: https://reviews.llvm.org/D22373

llvm-svn: 276875
2016-07-27 14:31:55 +00:00
Simon Pilgrim 10bf0ff879 [DAGCombiner] Use APInt directly to detect out of range shift constants
Using getZExtValue() will assert if the value doesn't fit into uint64_t - SHL was already doing this, I've just updated ASHR/LSHR to match

As mentioned on D22726

llvm-svn: 276855
2016-07-27 10:30:55 +00:00
Matt Arsenault e3862cdc93 AMDGPU: Use rcp for fdiv 1, x with fpmath metadata
Using rcp should be OK for safe math usually, so this
should not be replacing the original fdiv.

llvm-svn: 276823
2016-07-26 23:25:44 +00:00
Matt Arsenault 918e81c3d4 AMDGPU: Add more tests for LDS size with occupancy
llvm-svn: 276821
2016-07-26 23:15:59 +00:00
Matthias Braun 333e468d15 MIRParser: Use dot instead of colon to mark subregisters
Change the syntax to use `%0.sub8` to denote a subregister.

This seems like a more natural fit to denote subregisters; I also plan
to introduce a new ":classname" syntax in upcoming patches to denote the
register class of a vreg.

Note that this commit disallows plain identifiers to start with a '.'
character.  This shouldn't affect anything as external names/IR
references are all prefixed with '$'/'%', plain identifiers are only
used for instruction names, register mask names and subreg indexes.

Differential Revision: https://reviews.llvm.org/D22390

llvm-svn: 276815
2016-07-26 21:49:34 +00:00
Krzysztof Parzyszek 2a480599bb [Hexagon] Post-increment loads/stores enhancements
- Generate vector post-increment stores more aggressively.
- Predicate post-increment and vector stores in early if-conversion.

llvm-svn: 276800
2016-07-26 20:30:30 +00:00
Tim Northover ad2b717f2c GlobalISel: add generic load and store instructions.
Pretty straightforward, the only oddity is the MachineMemOperand (which it's
surprisingly difficult to share code for).

llvm-svn: 276799
2016-07-26 20:23:26 +00:00
Krzysztof Parzyszek 57c3ddddec [Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule
llvm-svn: 276793
2016-07-26 19:17:13 +00:00
Krzysztof Parzyszek 6eba5b8c37 [Hexagon] Rerun bit tracker on new instructions in RIE
Consider this case:
  vreg1 = A2_zxth vreg0   (1)
  ...
  vreg2 = A2_zxth vreg1   (2)

Redundant instruction elimination could delete the instruction (1)
because the user (2) only cares about the low 16 bits. Then it could
delete (2) because the input is already zero-extended. The problem
is that the properties allowing each individual instruction to be
deleted depend on the existence of the other instruction, so either
one can be deleted, but not both.
The existing check for this situation in RIE was insufficient. The
fix is to update all dependent cells when an instruction is removed
(replaced via COPY) in RIE.

llvm-svn: 276792
2016-07-26 19:08:45 +00:00
Krzysztof Parzyszek 1adca30c39 [Hexagon] Bitwise operations for insert/extract word not simplified
Change the bit simplifier to generate REG_SEQUENCE instructions in
addition to COPY, which will handle cases of word insert/extract.

llvm-svn: 276787
2016-07-26 18:30:11 +00:00
Justin Lebar 16da82f4d2 Fix NVPTX/call-with-alloca-buffer.ll after r276777.
r276777 makes InstSimplify stronger, letting it see through some
unnecessary addrspace casts.

llvm-svn: 276786
2016-07-26 18:28:33 +00:00
Matthias Braun ee0679207b MIRParser: Use shorter cfi identifiers
In an instruction like:
	CFI_INSTRUCTION .cfi_def_cfa ...
we can drop the '.cfi_' prefix since that should be obvious by the
context:
	CFI_INSTRUCTION def_cfa ...

While being a terser and cleaner syntax this also prepares to dropping
support for identifiers starting with a dot character so we can use it
for expressions.

Differential Revision: http://reviews.llvm.org/D22388

llvm-svn: 276785
2016-07-26 18:20:00 +00:00
Tim Northover ab395cb071 GlobalISel: add correct operand type to G_FRAME_INDEX instrs.
Frame indices should use "addFrameIndex", not "addImm".

llvm-svn: 276775
2016-07-26 17:42:40 +00:00
Krzysztof Parzyszek 29c567a3f0 [Hexagon] Add support for proper handling of H and L constraints
H -> High part of reg pair.
L -> Low part of reg pair.

Patch by Sundeep Kushwaha.

llvm-svn: 276773
2016-07-26 17:31:02 +00:00
Tim Northover 26e40bdb9b GlobalISel: omit braces on MachineInstr types when there's only one.
Tidies up the representation a bit in the common case.

llvm-svn: 276772
2016-07-26 17:28:01 +00:00
Matt Arsenault 07f65718bb AMDGPU: Add missing tests for xnack option for HSA
llvm-svn: 276765
2016-07-26 16:45:50 +00:00
Matt Arsenault 32fc527c65 AMDGPU: Add fp legacy instruction intrinsics
This could use some additional optimization work
to use mad/mac legacy.

llvm-svn: 276764
2016-07-26 16:45:45 +00:00
Simon Pilgrim 0280959c0d [X86][SSE] Added extra memory folding tests for cvtsd2ss intrinsic
SSE only fold partial reg update instructions when optsize is enabled

llvm-svn: 276743
2016-07-26 12:44:50 +00:00
Simon Pilgrim 019e102426 [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsics
Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding.

This was only unearthed when rL276102 started using the intrinsic again.....

llvm-svn: 276740
2016-07-26 10:41:28 +00:00
Simon Dardis 68a204ddc1 [mips] MIPS64R6 compact branch support
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct
MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that
map to the same instruction, extend compact branch support for the
corresponding 64bit branches.

Reviewers: dsanders

Differential Revision: https://reviews.llvm.org/D20164

llvm-svn: 276739
2016-07-26 10:25:07 +00:00
Renato Golin 32b165f561 [ARM] Saturation instructions are DSP-only
The saturation instructions appeared in v6T2, with DSP extensions, but they
were being accepted / generated on any, with the new introduction of the
saturation detection in the back-end. This commit restricts the usage to
DSP-enable only cores.

Fixes PR28607.

llvm-svn: 276701
2016-07-25 22:25:25 +00:00
Simon Pilgrim fa863fb2f1 [X86] Regenerate v2i256 shift legalization tests
llvm-svn: 276692
2016-07-25 21:14:22 +00:00
Simon Pilgrim 2d7735e428 [X86] Regenerate i64 shift legalization tests
llvm-svn: 276691
2016-07-25 21:11:45 +00:00
Tim Northover 7c9eba90ff GlobalISel: add generic casts to IRTranslator
This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the
IRTranslator. The first two are direct translations (with 2 MachineInstr types
each). Since LLT discards information, a bitcast might become trivial and we
emit a COPY in those cases instead.

llvm-svn: 276690
2016-07-25 21:01:29 +00:00
Tim Northover e2e0067352 GlobalISel[AArch64]: support pointer types in argument lowering.
They're basically i64 for AArch64, but we'll leave them intact for stranger
targets. Also add some tests for the (very few) other cases we can handle right
now.

llvm-svn: 276689
2016-07-25 21:01:17 +00:00
Jan Vesely b64c8925e9 AMDGPU: Remove read_workdim intrinsic
Differential revision: https://reviews.llvm.org/D22732

llvm-svn: 276682
2016-07-25 20:17:02 +00:00
Matt Arsenault e047b2598e AMDGPU: Fix missing verify-machineinstrs in control flow test
llvm-svn: 276679
2016-07-25 19:39:06 +00:00
Simon Pilgrim ce8d82775c [X86][SSE] Added 2048-bit vector comparison tests
Upper limit of what can be held in a <32 x i8> result

llvm-svn: 276666
2016-07-25 17:56:01 +00:00
Elena Demikhovsky 64e5f929d0 AVX-512: Fixed [US]INT_TO_FP selection for i1 vectors.
It failed with assertion before this patch.

Differential Revision: https://reviews.llvm.org/D22735

llvm-svn: 276648
2016-07-25 16:51:00 +00:00
Krzysztof Parzyszek 080bebd212 [Hexagon] Add target feature to generate long calls
llvm-svn: 276638
2016-07-25 14:42:11 +00:00
Sam Parker d5ca0a65b5 [ARM] Improve longMAC codegen test
Added thumb targets and dataflow checks to the longMAC test.

Differential Revision: https://reviews.llvm.org/D22684

llvm-svn: 276629
2016-07-25 10:11:00 +00:00
Simon Dardis 618975206e [mips] Optimize materialization of i64 constants
Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit
integer. This allows us to generate the same instructions for the
materialization of the same constants regardless the width of their
type.

Patch by: Vasileios Kalintiris

Contributions by: Simon Dardis

Reviewers: Daniel Sanders

Differential Review: https://reviews.llvm.org/D21689

llvm-svn: 276628
2016-07-25 09:57:28 +00:00
Sam Parker 68c71cd1e4 [ARM] Enable ISel of SMMLS for ARM and Thumb2
Use ISelDAGToDAG to recognise the SMMLS instruction pattern.

Differential Revision: https://reviews.llvm.org/D22562

llvm-svn: 276624
2016-07-25 09:20:20 +00:00
Craig Topper ce415ff9c5 [AVX512] Add load folding support for the unmasked forms of the FMA instructions.
llvm-svn: 276615
2016-07-25 07:20:35 +00:00
Craig Topper 318e40b6f7 [AVX512] Add some additional patterns so that we can fold broadcast loads in the first argument of an FMADD/FMSUB/FNMADD/FNMSUB/FMADDSUB/FMSUBADD node. Also add patterns to support all combinations of the broadcast input and the preserved input for masked versions.
llvm-svn: 276614
2016-07-25 07:20:31 +00:00
Craig Topper 6bcbf5338c [AVX512] Cleanup FMA operand order in patterns to match the VEX versions and to really be 213, 231, and 132.
llvm-svn: 276613
2016-07-25 07:20:28 +00:00
Simon Pilgrim a6878bdc0f [X86][SSE] Added PR27854 tests
llvm-svn: 276571
2016-07-24 16:39:50 +00:00
Simon Pilgrim b7d75fee74 [X86] Add shift double tests for PR14593
llvm-svn: 276570
2016-07-24 16:10:21 +00:00
Simon Pilgrim 381a0ade5a [X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'
As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing.

llvm-svn: 276569
2016-07-24 16:00:53 +00:00
Simon Pilgrim b2df2dc298 [X86] Add SHRD shift combine tests
llvm-svn: 276568
2016-07-24 15:47:44 +00:00
Simon Pilgrim 0ededcb344 [X86] Regenerate shift by parts tests
llvm-svn: 276567
2016-07-24 15:38:51 +00:00
Simon Pilgrim 114205076d [X86][SSE] Regenerate shifts tests
llvm-svn: 276566
2016-07-24 15:25:36 +00:00
Simon Pilgrim 30a7cc2e1f [X86][SSE] Regenerate SSE copysign tests
llvm-svn: 276565
2016-07-24 15:17:50 +00:00
Simon Pilgrim 7f1c1db73c [X86][AVX512VL] Added AVX512VL half2float vector conversions tests to demonstrate PR23941
llvm-svn: 276563
2016-07-24 13:01:51 +00:00