maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
294,265 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

529 Commits

Author SHA1 Message Date
Chris Lattner fd857daa0d Finish moving uncond br over to .td file, remove from .cpp file. 
llvm-svn: 24590
 2005-12-04 18:48:01 +00:00
Chris Lattner d9d18aff6a Define BR in the .td file now that Evan made tblgen smarter. 
llvm-svn: 24589
 2005-12-04 18:42:54 +00:00
Nate Begeman 048b26387b Represent the encoding of the SPR instructions as they actually are, so 
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521
 2005-11-29 22:42:50 +00:00
Nate Begeman c138118cdb Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516
 2005-11-29 08:04:45 +00:00
Nate Begeman 11fd6b22b1 Small tweaks noticed while on the plane. 
llvm-svn: 24492
 2005-11-26 22:39:34 +00:00
Nate Begeman 8492fd30ab Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489
 2005-11-23 05:29:52 +00:00
Chris Lattner bd9efdb64c disentangle call operands from branch operands a bit 
llvm-svn: 24400
 2005-11-17 19:16:08 +00:00
Chris Lattner 4b11fa284d Generate LA and ADDIS when possible. 
llvm-svn: 24395
 2005-11-17 17:52:01 +00:00
Chris Lattner 595088aa0f Add an initial hack at legalizing GlobalAddress into the appropriate nodes 
on Darwin to remove smarts from the isel.  This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file.  However, we can currently emit stuff like
this:  :)

        li r2, lo16(L_x$non_lazy_ptr)
        lis r3, ha16(L_x$non_lazy_ptr)
        lwzx r2, r3, r2

The obvious improvements will follow.

llvm-svn: 24390
 2005-11-17 07:30:41 +00:00
Chris Lattner 63ed749ce0 LI could theoretically be used for the lo-part of a global address, just like 
lis can be used for the high part.

llvm-svn: 24388
 2005-11-17 07:04:43 +00:00
Nate Begeman a171f6b20c Patch to clean up function call pseudos and support the BLA instruction, 
which branches to an absolute address.  This is required to support objc
direct dispatch.

llvm-svn: 24370
 2005-11-16 00:48:01 +00:00
Chris Lattner 5d6cb604de add support for branch on ordered/unordered. 
llvm-svn: 24067
 2005-10-28 20:32:44 +00:00
Chris Lattner 81ff73ec46 autogen undef 
llvm-svn: 23991
 2005-10-25 21:03:41 +00:00
Chris Lattner b439dad538 Allow pseudos to have patterns, no functionality change 
llvm-svn: 23988
 2005-10-25 20:58:43 +00:00
Chris Lattner 261009a4df Autogen fsel 
llvm-svn: 23987
 2005-10-25 20:55:47 +00:00
Chris Lattner cd7f101c9a Autogen a few new ppc-specific nodes 
llvm-svn: 23985
 2005-10-25 20:41:46 +00:00
Chris Lattner e296949fbe Instead of aborting if not a case we can handle specially, break out and 
let the generic code handle it.  This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.

also, reindent this code

llvm-svn: 23874
 2005-10-21 21:17:10 +00:00
Nate Begeman fd0d55ec69 Match rotate. This does actually match the rotates in an rc5 cipher, but I 
haven't seen it fire on our testsuite.

llvm-svn: 23863
 2005-10-21 06:36:18 +00:00
Nate Begeman 60bbe2d1e5 Add some more patterns for i64 on ppc 
llvm-svn: 23842
 2005-10-20 07:51:08 +00:00
Jim Laskey 74ab9960f2 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Nate Begeman 9f3c26c4ea Write patterns for the various shl and srl patterns that don't involve 
doing something clever.

llvm-svn: 23824
 2005-10-19 18:42:01 +00:00
Chris Lattner c16b0c387f now that tblgen is smarter, use integers directly. This should help Andrew too 
llvm-svn: 23818
 2005-10-19 04:32:04 +00:00
Chris Lattner 5b6f4dc623 Convert these cases to patterns 
llvm-svn: 23811
 2005-10-19 01:38:02 +00:00
Nate Begeman 9eaa6bac06 Woo, it kinda works. We now generate this atrociously bad, but correct, 
code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr

llvm-svn: 23809
 2005-10-19 01:12:32 +00:00
Nate Begeman 92e77502f3 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.

llvm-svn: 23803
 2005-10-19 00:05:37 +00:00
Chris Lattner 5a2fb9787b Fix the JIT encoding of LWA, LD, STD, and STDU. 
llvm-svn: 23787
 2005-10-18 16:51:22 +00:00
Nate Begeman 0b71e007ef First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.

llvm-svn: 23778
 2005-10-18 00:28:58 +00:00
Chris Lattner 286c1d7cfa Add a pattern for FSQRTS 
llvm-svn: 23750
 2005-10-15 21:44:15 +00:00
Chris Lattner 7503d46feb Rename PowerPC*.td -> PPC*.td 
llvm-svn: 23740
 2005-10-14 23:40:39 +00:00