2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
03a173eb71
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
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llvm-svn: 142669
2011-10-21 18:43:28 +00:00
e6d88c9a51
Nuke an #if0 that got accidentally left in.
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llvm-svn: 142658
2011-10-21 16:59:08 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
f18eec158c
Tidy up.
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llvm-svn: 142297
2011-10-17 22:41:42 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
34957911e7
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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llvm-svn: 141786
2011-10-12 17:34:41 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
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Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
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llvm-svn: 141682
2011-10-11 17:29:55 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
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llvm-svn: 141671
2011-10-11 15:59:20 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
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llvm-svn: 141592
2011-10-10 23:06:42 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
6e5778f7b1
ARM prefix asmparser operand kind enums for readability.
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llvm-svn: 141438
2011-10-07 23:24:09 +00:00
b8d9f51e4c
Improve ARM assembly parser diagnostic for unexpected tokens.
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Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
llvm-svn: 141380
2011-10-07 18:27:04 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
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llvm-svn: 141190
2011-10-05 17:16:40 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
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llvm-svn: 141046
2011-10-03 23:38:36 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
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llvm-svn: 141038
2011-10-03 22:30:24 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
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llvm-svn: 141025
2011-10-03 21:12:43 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
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llvm-svn: 140426
2011-09-23 22:25:02 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
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llvm-svn: 140125
2011-09-20 00:46:54 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
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llvm-svn: 140095
2011-09-19 23:31:02 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
8221319707
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
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llvm-svn: 140047
2011-09-19 20:29:33 +00:00
40700e0992
ARM asm parsing should handle pre-indexed writeback w/o immediate.
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For example, 'ldrb r9, [sp]!' is odd, but valid.
llvm-svn: 140035
2011-09-19 18:42:21 +00:00
d0c435c23c
Thumb2 assembly parsing and encoding for SUB(immediate).
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llvm-svn: 139966
2011-09-16 22:58:42 +00:00
9c0b86a76d
Thumb2 assembly parsing and encoding for STR.
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More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
099c9767c3
Thumb2 assembly parsing and encoding for STMIA.
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llvm-svn: 139938
2011-09-16 20:50:13 +00:00
d73c6458de
Thumb2 assembly parsing and encoding for SMMULL.
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llvm-svn: 139921
2011-09-16 18:05:48 +00:00
5e6d5cd7da
Kill some dead code.
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llvm-svn: 139904
2011-09-16 16:45:40 +00:00
6c45b75154
Tidy up a bit.
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llvm-svn: 139903
2011-09-16 16:39:25 +00:00
f9799d2c2d
Thumb2 assembly parsing and encoding for SMLAL.
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llvm-svn: 139902
2011-09-16 16:38:00 +00:00
d7791b961c
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
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llvm-svn: 139747
2011-09-14 22:46:14 +00:00
9c8b9932d6
Thumb2 assembly parsing and encoding for MUL.
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llvm-svn: 139735
2011-09-14 21:00:40 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
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Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
18b8b17579
Thumb2 assembly parsing for MOV in IT block.
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Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
3ac26b138b
ARM fix assembly parser handling of ranges in register lists.
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Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
75461af000
Remove unnecessary scope resolution operator.
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llvm-svn: 139656
2011-09-13 22:56:44 +00:00
e3a6a82f16
There's only 16 regs legal in a register list.
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llvm-svn: 139637
2011-09-13 20:35:57 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
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llvm-svn: 139610
2011-09-13 17:59:19 +00:00
3337e396c8
Tidy up a bit.
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llvm-svn: 139559
2011-09-12 23:36:42 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
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llvm-svn: 139399
2011-09-09 20:24:45 +00:00
Jim Grosbach