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Author SHA1 Message Date
JF Bastien 5ca0baca4a WebAssembly: basic instructions todo, and basic register info. 
Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11070

llvm-svn: 241923
 2015-07-10 18:23:10 +00:00
JF Bastien 03855df197 WebAssembly: start instructions 
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

llvm-svn: 241211
 2015-07-01 23:41:25 +00:00
Dan Gohman 10e730a263 [WebAssembly] Initial WebAssembly backend 
This WebAssembly backend is just a skeleton at this time and is not yet
functional.

llvm-svn: 241022
 2015-06-29 23:51:55 +00:00