ac5392c596
Fix a missing #include.
...
llvm-svn: 60458
2008-12-03 02:10:00 +00:00
0c8df671ac
Fix this comment to reflect that it applies to types other
...
than just i32.
llvm-svn: 60455
2008-12-03 01:39:44 +00:00
5d3d1f69e1
Fix byval arguments in the fastcc calling convention. The fastcc convention
...
delegates to the regular x86-32 convention which handles byval, but only
after it handles a few cases, and it's necessary to handle byval before
handling those cases. This fixes PR3122 (and rdar://6400815), llvm-gcc
miscompiling LLVM.
llvm-svn: 60453
2008-12-03 01:28:04 +00:00
7364025ff8
CellSPU:
...
- Incorporate Tilmann Scheller's ISD::TRUNCATE custom lowering patch
- Update SPU calling convention info, even if it's not used yet (but can be
at some point or another)
- Ensure that any-extended f32 loads are custom lowered, especially when
they're promoted for use in printf.
llvm-svn: 60438
2008-12-02 19:53:53 +00:00
0cdc0bbb8a
add a note
...
llvm-svn: 60404
2008-12-02 06:32:34 +00:00
85de4b35ca
- Remove the buggy -X/C -> X/-C transform. This isn't valid when X isn't a
...
constant. If X is a constant, then this is folded elsewhere.
- Added a note to Target/README.txt to indicate that we'd like to implement
this when we're able.
llvm-svn: 60399
2008-12-02 05:12:47 +00:00
30e9dc81c8
Second stab at target-dependent lowering of everyone's favorite nodes: [SU]ADDO
...
- LowerXADDO lowers [SU]ADDO into an ADD with an implicit EFLAGS define. The
EFLAGS are fed into a SETCC node which has the conditional COND_O or COND_C,
depending on the type of ADDO requested.
- LowerBRCOND now recognizes if it's coming from a SETCC node with COND_O or
COND_C set.
llvm-svn: 60388
2008-12-02 01:06:39 +00:00
122c515809
Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS".
...
llvm-svn: 60385
2008-12-02 00:07:05 +00:00
351b6659ad
Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail.
...
llvm-svn: 60383
2008-12-01 23:44:08 +00:00
a435b1aebc
- Have "ADD" instructions return an implicit EFLAGS.
...
- Add support for seto, setno, setc, and setnc instructions.
llvm-svn: 60382
2008-12-01 23:30:42 +00:00
08a4e2045d
CellSPU:
...
- Fix v2[if]64 vector insertion code before IBM files a bug report.
- Ensure that zero (0) offsets relative to $sp don't trip an assert
(add $sp, 0 gets legalized to $sp alone, tripping an assert)
- Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32
llvm-svn: 60358
2008-12-01 17:56:02 +00:00
3d960941b1
There are no longer any places that require a
...
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
llvm-svn: 60349
2008-12-01 11:41:29 +00:00
6ed40141f7
Change the interface to the type legalization method
...
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
llvm-svn: 60348
2008-12-01 11:39:25 +00:00
5b902c5b1e
Implement ((A|B)&1)|(B&-2) -> (A&1) | B transformation. This also takes care of
...
permutations of this pattern.
llvm-svn: 60312
2008-12-01 01:07:11 +00:00
de89bc275c
Add instruction combining for ((A&~B)|(~A&B)) -> A^B and all permutations.
...
llvm-svn: 60291
2008-11-30 13:52:49 +00:00
9eef421e12
Implement (A&((~A)|B)) -> A&B transformation in the instruction combiner. This
...
takes care of all permutations of this pattern.
llvm-svn: 60290
2008-11-30 13:08:13 +00:00
e9ef170d4a
A couple small cleanups, plus a new potential optimization.
...
llvm-svn: 60286
2008-11-30 07:52:27 +00:00
e16c0ff1d3
Moving potential optimizations out of PR2330 into lib/Target/README.txt.
...
Hopefully this isn't too much stuff to dump into this file.
llvm-svn: 60285
2008-11-30 07:36:04 +00:00
71ecd67b5d
Add include files needed when building with
...
gcc 4.4 (due to use of sprintf).
llvm-svn: 60209
2008-11-28 10:20:03 +00:00
595a4423dc
Fix build with gcc-4.4: it doesn't like PICStyle
...
being both a namespace and a variable name.
llvm-svn: 60208
2008-11-28 09:29:37 +00:00
edd5d3e4e9
Also update the README.
...
llvm-svn: 60188
2008-11-27 22:41:45 +00:00
b3dc4ad5b4
Add a synthetic missed optimization.
...
llvm-svn: 60186
2008-11-27 22:12:22 +00:00
128f032cc8
Comment out code that isn't entirely correct.
...
llvm-svn: 60156
2008-11-27 07:18:35 +00:00
b133907e61
Eliminate a compile time warning.
...
llvm-svn: 60145
2008-11-27 02:29:25 +00:00
83bdb38965
On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
...
e.g.
movl 4(%esp), %eax
addl $4, %eax
is 2 bytes shorter than
movl $4, %eax
addl 4(%esp), %eax
llvm-svn: 60139
2008-11-27 00:49:46 +00:00
751a694ad3
Generate something sensible for an [SU]ADDO op when the overflow/carry flag is
...
the conditional for the BRCOND statement. For instance, it will generate:
addl %eax, %ecx
jo LOF
instead of
addl %eax, %ecx
; About 10 instructions to compare the signs of LHS, RHS, and sum.
jl LOF
llvm-svn: 60123
2008-11-26 22:37:40 +00:00
fc371c6c1d
Cosmetic.
...
llvm-svn: 60110
2008-11-26 18:00:00 +00:00
83c70fa3dc
Emit declaration for globals and externs.
...
Custom lower AND, OR, XOR bitwise operations.
llvm-svn: 60098
2008-11-26 10:53:50 +00:00
002a2cb207
Fish kill flag annotations in PUSH instructions.
...
llvm-svn: 60095
2008-11-26 06:39:12 +00:00
ea0bd51cae
__fastcall and __stdcall are mingw extensions to gcc for windows. Use the
...
__attribute__ notation which is supported on more platforms.
llvm-svn: 60083
2008-11-26 03:17:27 +00:00
910046d174
CellSPU:
...
(a) Remove conditionally removed code in SelectXAddr. Basically, hope for the
best that the A-form and D-form address predicates catch everything before
the code decides to emit a X-form address.
(b) Expand vector store test cases to include the usual suspects.
llvm-svn: 60034
2008-11-25 17:29:43 +00:00
8e17d02a1e
CellSPU: Relax constraints on when to generate a X-form address, evidently
...
they were too tight according to bug 3126.
Fix bug 3126.
llvm-svn: 60006
2008-11-25 04:03:47 +00:00
524c284aef
CellSPU: Fix mnemonic typo in pattern; "shlqbyi" -> "shlqby".
...
llvm-svn: 59998
2008-11-25 00:23:16 +00:00
66835479d7
- Make lowering of "add with overflow" customizable by back-ends.
...
- Mark "add with overflow" as having a custom lowering for X86. Give it a null
lowering representation for now.
llvm-svn: 59971
2008-11-24 19:21:46 +00:00
2e5df906f8
CellSPU:
...
(a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to
directly zero-extend i32 to i64, but use rotates and shifts for
sign extension. Also ensure unified register consistency.
(b) Add new test harness for i64 operations: i64ops.ll
llvm-svn: 59970
2008-11-24 18:20:46 +00:00
efc8c7a292
CellSPU:
...
(a) Improve the extract element code: there's no need to do gymnastics with
rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.
llvm-svn: 59965
2008-11-24 17:11:17 +00:00
dc2dac181a
If the type legalizer actually legalized anything
...
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types. I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.
llvm-svn: 59960
2008-11-24 14:53:14 +00:00
75339657bd
Fix comments.
...
llvm-svn: 59958
2008-11-24 11:44:00 +00:00
977e7be9d4
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
...
llvm-svn: 59953
2008-11-24 07:34:46 +00:00
35a70ec131
Added missing description for -disable-mmx option.
...
llvm-svn: 59929
2008-11-24 02:10:43 +00:00
8d6e2e13d5
Rename SetCCResultContents to BooleanContents. In
...
practice these booleans are mostly produced by SetCC,
however the concept is more general.
llvm-svn: 59911
2008-11-23 15:47:28 +00:00
0aa8f0a549
Added -disable-mmx using a patch from Preston Gurd.
...
llvm-svn: 59901
2008-11-23 04:37:22 +00:00
0be0339baa
CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was it
...
ever conceived to occur).
llvm-svn: 59891
2008-11-22 23:50:42 +00:00
bff4b37af5
Make a convenient helper for printing offsets.
...
llvm-svn: 59872
2008-11-22 16:15:34 +00:00
c6918c1ffa
CellSPU:
...
(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.
llvm-svn: 59790
2008-11-21 02:56:16 +00:00
3726019aa3
CellSPU:
...
(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.
llvm-svn: 59734
2008-11-20 16:36:33 +00:00
e15a540071
Allow XMM2 and XMM3 to be used for non ABI compliant code.
...
llvm-svn: 59720
2008-11-20 07:48:19 +00:00
a7521ee3df
CellSPU: Custom lower truncating stores of i8 to i1 (should not have been
...
promote), fix signed conversion of indexed offsets.
llvm-svn: 59707
2008-11-20 05:01:09 +00:00
e361f08ab0
CellSPU: Adjust spacing/tabulation
...
llvm-svn: 59703
2008-11-20 04:26:21 +00:00
5f23e9fe73
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
...
llvm-svn: 59696
2008-11-20 02:25:51 +00:00
59213d64e5
Eliminate a compile time warning.
...
llvm-svn: 59678
2008-11-19 23:21:33 +00:00
dfb97383d5
Eliminate a compile time warning.
...
llvm-svn: 59677
2008-11-19 23:21:11 +00:00
60cb69e665
Experimental post-pass scheduling support. Post-pass scheduling
...
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
llvm-svn: 59676
2008-11-19 23:18:57 +00:00
7455d45ba2
CMake: Removed source file from lib/Target/PIC16/CMakeLists.txt.
...
llvm-svn: 59655
2008-11-19 18:42:25 +00:00
ef5e6934cb
CellSPU: Do not custom lower i1 stores, rely on type legalization to do the
...
right thing and promote the store to i8.
llvm-svn: 59648
2008-11-19 17:45:08 +00:00
0daa1b4a94
<rdar://problem/6351057>
...
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.
llvm-svn: 59644
2008-11-19 17:19:35 +00:00
3462c8ecda
Temporary check-in for Duncan to demonstrate CellSPU store problem.
...
llvm-svn: 59637
2008-11-19 15:24:16 +00:00
7e8bf3422f
Forgot to add this in the previous commit.
...
llvm-svn: 59623
2008-11-19 12:12:49 +00:00
5c63cf8bfd
Fixed build warnings.
...
llvm-svn: 59621
2008-11-19 11:27:59 +00:00
2ae21ee517
Added a more function PIC16 backend. However to get this working a patch in
...
ExpandIntegerOperand (LegalizeIntegerTypes.cpp) is needed which is yet to be reworked and submitted.
llvm-svn: 59617
2008-11-19 11:00:54 +00:00
c8d2b0135a
Don't set neverHasSideEffects on x86's divide instructions, since
...
they trap on divide-by-zero, and this side effect is otherwise
unmodeled.
llvm-svn: 59551
2008-11-18 21:29:14 +00:00
0b2732598c
Add more const qualifiers. This fixes build breakage from r59540.
...
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
aae3a4f864
Move some former testcases (low-probability codegen
...
optimizations) into this wishlist.
llvm-svn: 59455
2008-11-17 18:56:34 +00:00
ba4eb2a9db
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
...
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
llvm-svn: 59378
2008-11-15 21:36:30 +00:00
9c205bf03c
Fix fuitos encoding.
...
llvm-svn: 59344
2008-11-15 00:40:57 +00:00
30f6f8fdad
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
...
llvm-svn: 59314
2008-11-14 20:09:11 +00:00
80cd21dba6
Remove unneeded stuff from GRAD register class.
...
llvm-svn: 59311
2008-11-14 18:10:48 +00:00
0f802ba33e
[XCore] Remove whitespace in the description used when
...
registering XCoreTargetMachine.
llvm-svn: 59308
2008-11-14 16:19:56 +00:00
5fe5933909
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
...
these operations if ladd/lsub are not available on the current
subtarget.
llvm-svn: 59305
2008-11-14 15:59:19 +00:00
d16b37efae
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
...
bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
fabdcce677
Handle the rest of pseudo instructions.
...
llvm-svn: 59275
2008-11-13 23:36:57 +00:00
ea68423998
Lazy compilation callback save / restore VFP registers.
...
llvm-svn: 59274
2008-11-13 23:28:54 +00:00
bee1ad9707
Extend InlineAsm::C_Register to allow multiple specific registers
...
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
llvm-svn: 59266
2008-11-13 21:52:36 +00:00
935963de81
Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.
...
llvm-svn: 59258
2008-11-13 19:22:28 +00:00
320902bcfc
fsub{d|s} encoding bugs.
...
llvm-svn: 59234
2008-11-13 07:59:48 +00:00
4af89f7e7d
Missed a break statement.
...
llvm-svn: 59231
2008-11-13 07:46:59 +00:00
2666f59322
Fix pre- and post-indexed load / store encoding bugs.
...
llvm-svn: 59230
2008-11-13 07:34:59 +00:00
88ba5f0b96
Move the code that inserts X87 FP_REG_KILL instructions from a
...
special-purpose hook to a new pass. Also, add check to see if any
x87 virtual registers are used, to avoid doing any work in the
common case that no x87 code is needed.
llvm-svn: 59190
2008-11-12 22:55:05 +00:00
287a25d636
Remove the incorrect assertion. We don't have enough information before relocation to set U bit.
...
llvm-svn: 59170
2008-11-12 21:37:59 +00:00
45d030a05a
Address mode immediate offset has already been divided by 4.
...
llvm-svn: 59117
2008-11-12 08:21:12 +00:00
052f20d3b1
Fix a VFP binary arithmetic instruction encoding bug.
...
llvm-svn: 59116
2008-11-12 08:14:21 +00:00
2836d91630
Fix address mode 3 immediate offset mode encoding.
...
llvm-svn: 59109
2008-11-12 07:34:37 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
...
llvm-svn: 59107
2008-11-12 07:18:38 +00:00
4b6c7efbde
Fix VFP conversion instruction encodings.
...
llvm-svn: 59104
2008-11-12 06:41:41 +00:00
a0e2f26320
Fix encoding of single-precision VFP registers.
...
llvm-svn: 59102
2008-11-12 02:19:38 +00:00
bfcee5b863
VFP fld / fst immediate field is multiplied by 4.
...
llvm-svn: 59100
2008-11-12 01:02:24 +00:00
7d8b884b12
This shouldn't be necessary
...
llvm-svn: 59090
2008-11-11 23:19:51 +00:00
97ccab888a
Fix FMDRR encoding.
...
llvm-svn: 59088
2008-11-11 22:46:12 +00:00
ad519bbe54
Handle floating point constpool_entry's.
...
llvm-svn: 59087
2008-11-11 22:19:31 +00:00
8cbbcb1f2f
Encode VFP load / store instructions.
...
llvm-svn: 59084
2008-11-11 21:48:44 +00:00
38c9a14a88
Encode VFP conversion instructions.
...
llvm-svn: 59074
2008-11-11 19:40:26 +00:00
2d1937ede5
Add a README entry.
...
llvm-svn: 59052
2008-11-11 17:35:52 +00:00
a08c2905ad
CMake: corrected split of Alpha and Sparc AsmPrinters.
...
llvm-svn: 59050
2008-11-11 17:10:13 +00:00
03e084d482
Separate sparc asmprinter. This should unbreak the native build
...
llvm-svn: 59047
2008-11-11 16:42:57 +00:00
f4caceb668
Separate alpha asmprinter. This should unbreak native build.
...
llvm-svn: 59046
2008-11-11 16:42:17 +00:00
059c4fa8d8
The 32-bit displacement field in an x86 address is signed. Arrange for it
...
to be sign-extended when it is promoted to 64 bits for intermediate
offset calculations. The offset calculations are done as uint64_t so that
overflow conditions are well defined.
This fixes a problem which is currently hidden by the x86 AsmPrinter but
which was exposed by r58917 (which is temporarily reverted). See PR3027
for details.
llvm-svn: 59044
2008-11-11 15:52:29 +00:00
2126a6d3c4
fix another libgcc blocker
...
llvm-svn: 59026
2008-11-11 06:06:07 +00:00
aab89ca749
Unbreak the buildbot and back out (inadvertant) casting edits in CellSPU
...
backend.
llvm-svn: 59018
2008-11-11 03:06:06 +00:00
ac2af2fdb2
Encode VFP arithmetic instructions.
...
llvm-svn: 59016
2008-11-11 02:11:05 +00:00
abad22cf45
CellSPU: Fix bug 3606, as well as some ongoing work.
...
llvm-svn: 59009
2008-11-10 23:43:06 +00:00
02771dc473
Correct PIC function stub codegen.
...
llvm-svn: 59006
2008-11-10 23:14:47 +00:00
d3b33fea65
Fix indentation.
...
llvm-svn: 59004
2008-11-10 22:09:58 +00:00
58fb9135e2
Added CONVERT_RNDSAT (conversion with rounding and saturation) SDNode to
...
support targets that support these conversions. Users should avoid using
this node as the current targets don't generating code for it.
llvm-svn: 59001
2008-11-10 20:54:11 +00:00
9f3058f3be
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
...
llvm-svn: 58949
2008-11-10 01:08:07 +00:00
cfb3bc4a45
Typo fix
...
llvm-svn: 58928
2008-11-09 02:54:13 +00:00
9833d8c369
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
...
and breaks llvm-gcc
llvm-svn: 58926
2008-11-08 23:05:05 +00:00
4829941a51
CMake: corrected library target name for dependency: LLVMCellSPU ->
...
LLVMCellSPUCodeGen.
llvm-svn: 58925
2008-11-08 21:23:15 +00:00
676e5194d0
CMake: Reflected changes on the CellSPU target build. May require a
...
clean start.
llvm-svn: 58924
2008-11-08 20:37:19 +00:00
b200b648c4
Fixed a pasto.
...
llvm-svn: 58923
2008-11-08 20:34:18 +00:00
a872e5af8a
CellSPU: Bring SPU's assembly printer more in-line with current LLVM code
...
structure. Assembly printer now outputs the correct section for strings.
llvm-svn: 58921
2008-11-08 18:59:02 +00:00
09f51d1fd4
Factor out offset printing code into generic AsmPrinter.
...
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
llvm-svn: 58917
2008-11-08 17:21:38 +00:00
5a48f232f7
The Index field of an AttributeWithIndex is of type unsigned, not uint16_t.
...
llvm-svn: 58908
2008-11-08 15:36:01 +00:00
09991ada2d
StoreInst does not produce any result thus it's useless to create new
...
variable for it. This greatly reduces amount of unused variables in
llvm2cpp-generated code
llvm-svn: 58905
2008-11-08 12:58:07 +00:00
436bdcdcca
Moved InvalidateInstructionCache to ARMJITInfo::emitFunctionStub which knows size of stub.
...
llvm-svn: 58899
2008-11-08 08:16:49 +00:00
b31a717527
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
...
llvm-svn: 58897
2008-11-08 08:02:53 +00:00
98161f5f34
Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
...
llvm-svn: 58896
2008-11-08 07:38:22 +00:00
bb373c4637
Fix relocation for calls to external symbols.
...
llvm-svn: 58893
2008-11-08 07:22:33 +00:00
1ccbbc3d07
CellSPU: Fix prologue/epilogue emission when function contains calls but
...
theframe size is 0; the prologue and epilogue should be emitted in this case.
llvm-svn: 58890
2008-11-08 05:16:20 +00:00
077c8f8832
Skip over two-address use operands.
...
llvm-svn: 58883
2008-11-08 01:44:13 +00:00
ffdd91e3b8
Handle ARM machine constantpool entry with non-lazy ptr.
...
llvm-svn: 58882
2008-11-08 01:31:27 +00:00
454ff53d58
Use ARMFunctionInfo to track number of constpool entries and jumptables.
...
llvm-svn: 58877
2008-11-08 00:51:41 +00:00
ef4d78ba67
More code clean up.
...
llvm-svn: 58872
2008-11-07 22:57:53 +00:00
160be0ffda
Make FP tests requiring two compares work on PPC (PR 642).
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This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
llvm-svn: 58871
2008-11-07 22:54:33 +00:00
8467e2459a
Get PIC jump table working.
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llvm-svn: 58869
2008-11-07 22:30:53 +00:00
cb0df597e0
Flush the raw_ostream after emitting the assembly for a function.
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This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
llvm-svn: 58859
2008-11-07 19:49:17 +00:00
3219819ffe
Fix compile warnings.
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llvm-svn: 58840
2008-11-07 11:21:09 +00:00
3395d4485d
CellSPU: Ensure that C strings are always put in the .rodata section
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llvm-svn: 58839
2008-11-07 11:06:44 +00:00
ca08e0645a
Add XCore backend.
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llvm-svn: 58838
2008-11-07 10:59:00 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
34d93f8572
Teach CellSPU about ELF sections and new section emitter classes.
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NB: This is likely to need more work.
llvm-svn: 58832
2008-11-07 04:36:25 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
9a8d60a7c0
Widening cleanup
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llvm-svn: 58796
2008-11-06 05:31:54 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
b870fd8874
Fix so_imm encoding bug; add support for MOVi2pieces.
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llvm-svn: 58790
2008-11-06 02:25:39 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
7a638a8c7e
Reintroduce a comment that was removed with the AddToISelQueue
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changes.
llvm-svn: 58760
2008-11-05 17:16:24 +00:00
bfd58d87f3
Test commit, add Makefile for XCore target, more to follow.
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llvm-svn: 58755
2008-11-05 09:53:58 +00:00
27889ab29f
Add more vector move low and zero-extend patterns.
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llvm-svn: 58752
2008-11-05 06:04:51 +00:00
3cd5e8c97b
Indentation.
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llvm-svn: 58750
2008-11-05 06:03:38 +00:00
f14b77ebf1
Eliminate the ISel priority queue, which used the topological order for a
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priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
llvm-svn: 58748
2008-11-05 04:14:16 +00:00
fd820528ab
Use getTargetConstant instead of getConstant for nodes that should not be visited
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by isel and potentially forced into registers.
llvm-svn: 58747
2008-11-05 02:06:09 +00:00
132de1983f
Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X
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indirect gv reference. Please don't call it lazy.
llvm-svn: 58746
2008-11-05 01:50:32 +00:00
e3827d9061
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
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llvm-svn: 58725
2008-11-04 22:19:55 +00:00
297b32a367
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
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llvm-svn: 58714
2008-11-04 19:57:48 +00:00
4eaff40147
Debug output tweak.
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llvm-svn: 58708
2008-11-04 17:58:53 +00:00
Dan Gohman