llvm-project

Author	SHA1	Message	Date
David Green	9f15fcc271	[ARM] Replace arm_neon_vqadds with sadd_sat This replaces the A32 NEON vqadds, vqaddu, vqsubs and vqsubu intrinsics with the target independent sadd_sat, uadd_sat, ssub_sat and usub_sat. This helps generate vqadds from standard IR nodes, which might be produced from the vectoriser. The old variants are removed in the process. Differential Revision: https://reviews.llvm.org/D69350	2019-11-27 13:32:29 +00:00
Eric Christopher	53b2cb77cc	Unified logic for computing target ABI in backend and front end by moving this common code to Support/TargetParser. Modeled Triple::GNU after front end code (aapcs abi) and updated tests that expect apcs abi. Patch by Ana Pazos! llvm-svn: 306769	2017-06-30 00:03:56 +00:00
Alexandros Lamprineas	d162b5c8c4	[ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics. Differential Revision: http://reviews.llvm.org/D15223 llvm-svn: 256822	2016-01-05 09:58:29 +00:00
NAKAMURA Takumi	704b795634	clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c REQUIRES both arm and aarch64. llvm-svn: 254252	2015-11-29 13:43:05 +00:00
Alexandros Lamprineas	cd8d973932	ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract. Add missing tests that accidentally were not committed in rL254250. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254251	2015-11-29 10:53:28 +00:00