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Author SHA1 Message Date
Alex Lorenz 36962cd925 MIR Parser: Verify the implicit machine register operands. 
This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781

llvm-svn: 241537
 2015-07-07 02:08:46 +00:00