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Author SHA1 Message Date
Chris Lattner cd92718a0f use assertions instead of unreachable for logic errors. 
llvm-svn: 100724
 2010-04-07 23:47:51 +00:00
Chris Lattner 1e45789ee0 introduce a new recoverable error handling API to LLVMContext 
and use it in one place in inline asm handling stuff.  Before
we'd generate this for an invalid modifier letter:

$ clang asm.c -c -o t.o
fatal error: error in backend: Invalid operand found in inline asm: 'abc incl    ${0:Z}'
INLINEASM <es:abc incl    ${0:Z}>, 10, %EAX<def>, 2147483657, %EAX, 14, %EFLAGS<earlyclobber,def,dead>, <!-1>


Now we generate this:

$ clang asm.c -c -o t.o
error: invalid operand in inline asm: 'incl    ${0:Z}'
asm.c:3:12: note: generated from here
  __asm__ ("incl    %Z0" : "+r" (X));
           ^
1 error generated.

This is much better but still admittedly not great ("why" is the operand 
invalid??), codegen should try harder with its diagnostics :)

llvm-svn: 100723
 2010-04-07 23:40:44 +00:00
Dan Gohman eb7111b98f Say bitcast instead of bitconvert. 
llvm-svn: 100720
 2010-04-07 23:22:42 +00:00
Chris Lattner 59c5753174 rename llvm_install_error_handler -> install_fatal_error_handler 
and friends.

llvm-svn: 100717
 2010-04-07 23:12:29 +00:00
Ted Kremenek 4b1b4205ed Update CMake build. 
llvm-svn: 100714
 2010-04-07 23:05:23 +00:00
Benjamin Kramer 33f6413c58 Update cmake build. 
llvm-svn: 100713
 2010-04-07 23:01:37 +00:00
Eric Christopher e8b281c3c3 Add support for stpncpy_chk. 
llvm-svn: 100710
 2010-04-07 23:00:07 +00:00
Chris Lattner 2104b8d36e rename llvm::llvm_report_error -> llvm::report_fatal_error 
llvm-svn: 100709
 2010-04-07 22:58:41 +00:00
Chris Lattner 5109d3e55d add newlines at end of files. 
llvm-svn: 100706
 2010-04-07 22:54:55 +00:00
Chris Lattner cc7bb24fe2 remove some unneeded errorhandling stuff. 
llvm-svn: 100703
 2010-04-07 22:44:07 +00:00
Chris Lattner b6166b372e minor tidying up 
llvm-svn: 100702
 2010-04-07 22:41:29 +00:00
Chris Lattner b50e795369 tidy up 
llvm-svn: 100700
 2010-04-07 22:29:10 +00:00
Dan Gohman d006ab90dd Generalize IVUsers to track arbitrary expressions rather than expressions 
explicitly split into stride-and-offset pairs. Also, add the
ability to track multiple post-increment loops on the same expression.

This refines the concept of "normalizing" SCEV expressions used for
to post-increment uses, and introduces a dedicated utility routine for
normalizing and denormalizing expressions.

This fixes the expansion of expressions which are post-increment users
of more than one loop at a time. More broadly, this takes LSR another
step closer to being able to reason about more than one loop at a time.

llvm-svn: 100699
 2010-04-07 22:27:08 +00:00
Johnny Chen 85ce9f4f30 Missed this one line for the previous checkin to fix build warnings. 
llvm-svn: 100697
 2010-04-07 22:21:03 +00:00
Johnny Chen 8b04b550df Fixed warnings pointed out by clang. 
llvm-svn: 100696
 2010-04-07 22:03:27 +00:00
Johnny Chen 80f8c3d533 Fixed warnings pointed out by clang. 
Next to work on is ARMDisassemblerCore.cpp.

llvm-svn: 100695
 2010-04-07 21:52:48 +00:00
Sean Callanan 1efe661b46 Fixed a bug where the disassembler would allow an immediate 
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694
 2010-04-07 21:42:19 +00:00
Johnny Chen 3f253e2cb1 Fixed 3 warnings pointed out by clang. 
llvm-svn: 100693
 2010-04-07 21:23:48 +00:00
Johnny Chen 4e2f8722c4 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in 
ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690
 2010-04-07 20:53:12 +00:00
Sean Callanan 643a55708f Added an AsmLexer for the ARM target, which uses 
a simple mapping of register names to IDs to
identify register tokens.

llvm-svn: 100685
 2010-04-07 20:29:34 +00:00
Dale Johannesen 60b289709e Educate GetInstrSizeInBytes implementations that 
DBG_VALUE does not generate code.

llvm-svn: 100681
 2010-04-07 19:51:44 +00:00
Gabor Greif 08d85da6cc fix 80-col violations 
llvm-svn: 100677
 2010-04-07 18:59:26 +00:00
Anton Korobeynikov 6e01726eae Remove late ARM codegen optimization pass committed by accident. 
It is not ready for public yet.

llvm-svn: 100673
 2010-04-07 18:23:27 +00:00
Anton Korobeynikov 090323aee5 Split A8/A9 itins - they already were too big. 
llvm-svn: 100672
 2010-04-07 18:22:11 +00:00
Anton Korobeynikov 32457d6c5e Add some crude itin approximation for VFP load / stores on A9 
llvm-svn: 100671
 2010-04-07 18:22:03 +00:00
Anton Korobeynikov d351104f19 Add some crude approximation for neon load/store instructions 
llvm-svn: 100670
 2010-04-07 18:21:58 +00:00
Anton Korobeynikov 4acfad7c1b Add some A8-based approximation for instructions with unknown cycle times 
llvm-svn: 100669
 2010-04-07 18:21:52 +00:00
Anton Korobeynikov 4fb6a66c8f Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it. 
llvm-svn: 100668
 2010-04-07 18:21:46 +00:00
Anton Korobeynikov 982f0ceaf8 Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. 
llvm-svn: 100667
 2010-04-07 18:21:41 +00:00
Anton Korobeynikov 4050d69dcf Fix A8 FP NEON MAC itins 
llvm-svn: 100666
 2010-04-07 18:21:33 +00:00
Anton Korobeynikov 9ff2f8f7a5 A9 NEON FP itins 
llvm-svn: 100665
 2010-04-07 18:21:27 +00:00
Anton Korobeynikov 03b317a286 Some permute goodness for A9 
llvm-svn: 100664
 2010-04-07 18:21:22 +00:00
Anton Korobeynikov 7ab31047a7 More shift itins for A9 
llvm-svn: 100663
 2010-04-07 18:21:16 +00:00
Anton Korobeynikov 4d36f8890f More fixes for itins 
llvm-svn: 100662
 2010-04-07 18:21:10 +00:00
Anton Korobeynikov ceb54d5ab0 Fix invalid itins for 32-bit varians of VMLAL and friends 
llvm-svn: 100661
 2010-04-07 18:21:04 +00:00
Anton Korobeynikov f64c7ca5c3 Add MAC stuff for A9 
llvm-svn: 100660
 2010-04-07 18:20:58 +00:00
Anton Korobeynikov 2ef0a12fa1 Fix invalid NEON MAC itins on A8 
llvm-svn: 100659
 2010-04-07 18:20:53 +00:00
Anton Korobeynikov 5e208dc21b Fix itins for VPAL 
llvm-svn: 100658
 2010-04-07 18:20:47 +00:00
Anton Korobeynikov a248becd6c Fix itins for VABA 
llvm-svn: 100657
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov a3e4989ad8 Correct VMVN itinerary: operand is read in the second cycle, not in the first. 
llvm-svn: 100656
 2010-04-07 18:20:36 +00:00
Anton Korobeynikov 140a65ce0b More A9 itineraries 
llvm-svn: 100655
 2010-04-07 18:20:29 +00:00
Anton Korobeynikov 1a1af5a830 Correct itinerary class for VPADD 
llvm-svn: 100654
 2010-04-07 18:20:24 +00:00
Anton Korobeynikov 4650fd5fc6 VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. 
llvm-svn: 100653
 2010-04-07 18:20:18 +00:00
Anton Korobeynikov 7d4fad5942 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
llvm-svn: 100652
 2010-04-07 18:20:13 +00:00
Anton Korobeynikov 2cba05bbe1 Some easy NEON scheduling goodness for A9 
llvm-svn: 100651
 2010-04-07 18:20:07 +00:00
Anton Korobeynikov 2063705d91 Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
llvm-svn: 100650
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov c1e7a6feac FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9. 
llvm-svn: 100649
 2010-04-07 18:19:56 +00:00
Anton Korobeynikov dad973334b Proper cycle times for locks, since wbck latency can be larger than fwd latency. 
llvm-svn: 100648
 2010-04-07 18:19:51 +00:00
Anton Korobeynikov 4c1da0f82a Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
llvm-svn: 100647
 2010-04-07 18:19:46 +00:00
Anton Korobeynikov baeb210be7 Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. 
llvm-svn: 100646
 2010-04-07 18:19:40 +00:00