Commit Graph

49 Commits

Author SHA1 Message Date
Joerg Sonnenberger 635debe85b Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 

llvm-svn: 166712
2012-10-25 20:33:17 +00:00
Sean Silva 88eb8dd4ed tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.

llvm-svn: 165647
2012-10-10 20:24:47 +00:00
Sean Silva fb509ed156 tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

llvm-svn: 165646
2012-10-10 20:24:43 +00:00
Sean Silva 98c61711c6 tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of
these uses are actually more like isa<> or cast<>, and will be changed
to the semanticaly appropriate one in a future patch.

llvm-svn: 165291
2012-10-05 03:31:58 +00:00
Jim Grosbach 4c36349de9 TableGen: Add initializer.
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

llvm-svn: 164041
2012-09-17 18:00:53 +00:00
Michael Liao 026f833368 Re-work bit/bits value resolving in tblgen
- This patch is inspired by the failure of the following code snippet
  which is used to convert enumerable values into encoding bits to
  improve the readability of td files.

  class S<int s> {
    bits<2> V = !if(!eq(s, 8),  {0, 0},
                !if(!eq(s, 16), {0, 1},
                !if(!eq(s, 32), {1, 0},
                !if(!eq(s, 64), {1, 1}, {?, ?}))));
  }

  Later, PR8330 is found to report not exactly the same bug relevant
  issue to bit/bits values.

- Instead of resolving bit/bits values separately through
  resolveBitReference(), this patch adds getBit() for all Inits and
  resolves bit value by resolving plus getting the specified bit. This
  unifies the resolving of bit with other values and removes redundant
  logic for resolving bit only. In addition,
  BitsInit::resolveReferences() is optimized to take advantage of this
  origanization by resolving VarBitInit's variable reference first and
  then getting bits from it.

- The type interference in '!if' operator is revised to support possible
  combinations of int and bits/bit in MHS and RHS.

- As there may be illegal assignments from integer value to bit, says
  assign 2 to a bit, but we only check this during instantiation in some
  cases, e.g.

  bit V = !if(!eq(x, 17), 0, 2);

  Verbose diagnostic message is generated when invalid value is
  resolveed to help locating the error.

- PR8330 is fixed as well.

llvm-svn: 163360
2012-09-06 23:32:48 +00:00
Craig Topper 29688ab27c Declare some for loop indices inside the for loop statement.
llvm-svn: 162085
2012-08-17 05:42:16 +00:00
Craig Topper ebc3aa250b Fix up indentation of outputted decode function for readability.
llvm-svn: 162082
2012-08-17 05:16:15 +00:00
Benjamin Kramer 26b568d9d5 Fix a const violation in the generated disassembler.
llvm-svn: 161940
2012-08-15 10:26:44 +00:00
Jim Grosbach ecaef49f59 Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888
2012-08-14 19:06:05 +00:00
Jakob Stoklund Olesen e6aed139f0 Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311
2012-06-11 15:37:55 +00:00
Silviu Baranga 98144e9e1a Second part for the 153874 one
llvm-svn: 153875
2012-04-02 15:46:46 +00:00
Craig Topper 501d95c176 More const-correcting of FixedLenDecoderEmitter.
llvm-svn: 152906
2012-03-16 06:52:56 +00:00
Craig Topper 48c112babe Const-correct the FixedLenDecoderEmitter. Pass a few things by const reference instead of value to avoid some copying.
llvm-svn: 152899
2012-03-16 05:58:09 +00:00
Craig Topper 82d0d5fc6b Spacing fixes. Mostly aligning arguments that spilled onto next line with the opening parenthese instead of 2 spaces in.
llvm-svn: 152889
2012-03-16 01:19:24 +00:00
Craig Topper 93e6434ca9 Remove unused field NumVariable from Filter class. Even it was needed the same result could be found with VariableInstructions.size(). Also fix some typos in comments.
llvm-svn: 152885
2012-03-16 00:56:01 +00:00
Craig Topper ba6d810752 Remove unused field from FixedLenDecoderEmitter. Move NumberedInstructions declaration from class to run method since its only used there and was being reinitialized anyway.
llvm-svn: 152616
2012-03-13 06:39:00 +00:00
Jim Grosbach 3f4b23933f Tidy up. 80 columns.
llvm-svn: 151764
2012-02-29 22:07:56 +00:00
James Molloy d9ba4fd48f Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
llvm-svn: 150169
2012-02-09 10:56:31 +00:00
Craig Topper c4965bce14 Convert assert(0) to llvm_unreachable
llvm-svn: 149814
2012-02-05 07:21:30 +00:00
Owen Anderson b7d9ee707d Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.
llvm-svn: 142193
2011-10-17 16:56:47 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Bob Wilson ce29158bc4 Subtarget getFeatureBits() returns a uint64_t, not unsigned.
llvm-svn: 140928
2011-10-01 02:47:54 +00:00
Eli Friedman e776b580c1 Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
llvm-svn: 139317
2011-09-08 21:00:31 +00:00
James Molloy 21d293a37f Fix warning on windows; use of comparison with bool argument.
llvm-svn: 139286
2011-09-08 08:12:01 +00:00
Andrew Trick 43674ad44d Fix a use of freed string contents.
Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279
2011-09-08 05:25:49 +00:00
Andrew Trick 61abca6daa whitespace
llvm-svn: 139278
2011-09-08 05:23:14 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Owen Anderson ecc4ffc941 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
llvm-svn: 137171
2011-08-09 23:05:23 +00:00
Owen Anderson 3022d6711d Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.
llvm-svn: 136660
2011-08-01 22:45:43 +00:00
Owen Anderson faee2cf9ff The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.
llvm-svn: 136645
2011-08-01 20:06:49 +00:00
Owen Anderson 37ef826040 Enhance the fixed length disassembler to better handle operand decoding failures.
llvm-svn: 136635
2011-08-01 18:44:37 +00:00
Owen Anderson e08f5b5b37 Correctly handle scattered operands where the bits of the operand are contiguous, but out of order.
llvm-svn: 136534
2011-07-29 23:01:18 +00:00
David Greene af8ee2cdee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene 1aa0e3e118 [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
Owen Anderson cb32ce2642 Third time's the charm for implementing tied operand decoding properly.
llvm-svn: 136478
2011-07-29 18:28:52 +00:00
Owen Anderson abe75904a8 Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping.
llvm-svn: 136467
2011-07-29 17:32:03 +00:00
Owen Anderson 53562d0551 Enhance the fixed-length decoder emitter to support tied operands.
llvm-svn: 136431
2011-07-28 23:56:20 +00:00
Owen Anderson e3591657a0 Enhance the fixed-length decoder emitter to support parsing scattered fields.
llvm-svn: 136405
2011-07-28 21:54:31 +00:00
Owen Anderson c78e03c39a Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
Eric Christopher 71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene af973b4f36 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Jim Grosbach f3fd36e0f5 Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
2011-07-06 21:33:38 +00:00
Owen Anderson a84be6c96b Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940
2011-06-27 21:06:21 +00:00
Owen Anderson f2e8397b4b Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
llvm-svn: 129708
2011-04-18 18:42:26 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Owen Anderson 0fabf10388 Ignore isCodeGenOnly instructions when generating diassembly tables.
llvm-svn: 127619
2011-03-14 20:58:49 +00:00
Owen Anderson 4e81890d36 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966
2011-02-18 21:51:29 +00:00