Commit Graph

91 Commits

Author SHA1 Message Date
Evandro Menezes 03789a9ec7 Fix issue with invalid flat operand number
Avoid iterating over list of operands beyond the number of operands in it.

PS: this fixes issue with revision #167634.
llvm-svn: 167635
2012-11-09 21:27:03 +00:00
Evandro Menezes 567698a6ca Fix issue with invalid flat operand number
Avoid iterating over list of operands beyond the number of operands in it.

llvm-svn: 167634
2012-11-09 20:29:37 +00:00
Sean Silva fb509ed156 tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

llvm-svn: 165646
2012-10-10 20:24:43 +00:00
Michael Liao 026f833368 Re-work bit/bits value resolving in tblgen
- This patch is inspired by the failure of the following code snippet
  which is used to convert enumerable values into encoding bits to
  improve the readability of td files.

  class S<int s> {
    bits<2> V = !if(!eq(s, 8),  {0, 0},
                !if(!eq(s, 16), {0, 1},
                !if(!eq(s, 32), {1, 0},
                !if(!eq(s, 64), {1, 1}, {?, ?}))));
  }

  Later, PR8330 is found to report not exactly the same bug relevant
  issue to bit/bits values.

- Instead of resolving bit/bits values separately through
  resolveBitReference(), this patch adds getBit() for all Inits and
  resolves bit value by resolving plus getting the specified bit. This
  unifies the resolving of bit with other values and removes redundant
  logic for resolving bit only. In addition,
  BitsInit::resolveReferences() is optimized to take advantage of this
  origanization by resolving VarBitInit's variable reference first and
  then getting bits from it.

- The type interference in '!if' operator is revised to support possible
  combinations of int and bits/bit in MHS and RHS.

- As there may be illegal assignments from integer value to bit, says
  assign 2 to a bit, but we only check this during instantiation in some
  cases, e.g.

  bit V = !if(!eq(x, 17), 0, 2);

  Verbose diagnostic message is generated when invalid value is
  resolveed to help locating the error.

- PR8330 is fixed as well.

llvm-svn: 163360
2012-09-06 23:32:48 +00:00
Jakob Stoklund Olesen e6aed139f0 Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311
2012-06-11 15:37:55 +00:00
NAKAMURA Takumi c72fdf4490 TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.
~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF.

llvm-svn: 152407
2012-03-09 14:52:44 +00:00
Owen Anderson 773642d3d8 Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this.
llvm-svn: 152148
2012-03-06 21:48:32 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
David Greene af8ee2cdee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene e32ebf220a [AVX] Create Inits Via Factory Method
Replace uses of new *Init with *Init::get.  This hides the allocation
implementation so that we can unique Inits in various ways.

llvm-svn: 136486
2011-07-29 19:07:07 +00:00
David Greene 1aa0e3e118 [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
David Greene b3da8123c0 [AVX] Remove Mutating Members from Inits
Get rid of all Init members that modify internal state.  This is in
preparation for making references to Inits const.

llvm-svn: 136483
2011-07-29 19:07:00 +00:00
Eric Christopher 71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene cf8a603a1b Use get(0 Instead of Create()
Respond to some feedback asking for a name change.

llvm-svn: 134921
2011-07-11 20:55:22 +00:00
David Greene af973b4f36 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Jim Grosbach f3fd36e0f5 Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
2011-07-06 21:33:38 +00:00
Owen Anderson 715973fc6c Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>

llvm-svn: 130410
2011-04-28 17:51:45 +00:00
Jim Grosbach cd25b86fb9 Tidy up a bit.
llvm-svn: 124832
2011-02-03 23:26:36 +00:00
Bob Wilson f9bab3a47a Fix a comment typo.
llvm-svn: 124450
2011-01-27 23:08:52 +00:00
Jeffrey Yasskin 9b43f33620 Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
2010-12-23 00:58:24 +00:00
Bill Wendling 5343836f2d Move <map> include out of .h and into .cpp.
llvm-svn: 121661
2010-12-13 01:05:54 +00:00
Chris Lattner 77d369c8eb eliminate the Records global variable, patch by Garrison Venn!
llvm-svn: 121659
2010-12-13 00:23:57 +00:00
Chris Lattner 578c765fc8 pull the code to get the operand value out of the loop.
llvm-svn: 119130
2010-11-15 07:09:28 +00:00
Chris Lattner c19d510363 split the giant encoder loop into two new helper functions.
llvm-svn: 119129
2010-11-15 06:59:17 +00:00
Chris Lattner 42c4ac4841 reduce nesting and minor cleanups, no functionality change.
llvm-svn: 119128
2010-11-15 06:42:13 +00:00
Chris Lattner 63274cbc5d add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
2010-11-15 05:19:05 +00:00
Owen Anderson c88ce8329c Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
Not yet used.

llvm-svn: 118759
2010-11-11 01:19:24 +00:00
Jim Grosbach e4e6bf49f3 Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
Fixups list for the instruction so the operand encoders can add to it as
needed.

llvm-svn: 118206
2010-11-03 23:38:14 +00:00
Jim Grosbach 0b7fda23cc Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
2010-11-02 17:35:25 +00:00
Jim Grosbach 9a33835caa Tidy up.
llvm-svn: 117987
2010-11-02 00:16:39 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Jim Grosbach 51a12eb11d Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

llvm-svn: 116353
2010-10-12 22:21:57 +00:00
Jim Grosbach e61de930bc The assert() should reference to machine instr operand number, too.
llvm-svn: 116243
2010-10-11 21:41:31 +00:00
Jim Grosbach 11ced671be Make sure to use the machine instruction operand number. It doesn't always
map one-to-one with the CodeGenInstruction operand number.

llvm-svn: 116238
2010-10-11 21:31:22 +00:00
Jim Grosbach 191ad7c473 When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).

llvm-svn: 116211
2010-10-11 18:25:51 +00:00
Jim Grosbach a7b6d58f45 Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Jim Grosbach daab660fb1 trailing whitespace
llvm-svn: 115923
2010-10-07 16:56:28 +00:00
Jakob Stoklund Olesen 3b1657b777 Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

llvm-svn: 107520
2010-07-02 21:44:22 +00:00
Evan Cheng 66561537f5 Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026

llvm-svn: 102815
2010-05-01 00:28:44 +00:00
Chris Lattner 2104b8d36e rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Chris Lattner 918be520dc change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910
2010-03-19 00:34:35 +00:00
Chris Lattner 9aec14b560 look up instructions by record, not by name.
llvm-svn: 98904
2010-03-19 00:07:20 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Dale Johannesen 881ba0bb92 Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.

llvm-svn: 93498
2010-01-15 01:50:44 +00:00
Dale Johannesen 237254dcab Add DEBUG_DECLARE. Not used yet.
llvm-svn: 93040
2010-01-09 01:24:25 +00:00
Dale Johannesen 8f04740650 Add DEBUG_VALUE. Not used yet.
llvm-svn: 93030
2010-01-08 23:51:25 +00:00
Dan Gohman c87c16b030 Revert 90628, which was incorrect.
llvm-svn: 91448
2009-12-15 20:21:44 +00:00
Dan Gohman e79368d3ff Minor code simplification.
llvm-svn: 90628
2009-12-05 00:05:43 +00:00
Jakob Stoklund Olesen dc9efe8078 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006
2009-09-28 20:32:26 +00:00