Commit Graph

9 Commits

Author SHA1 Message Date
Martin Storsjö d5c5cf5ce8 [AArch64] [COFF] Properly produce cross-section relative relocations
This fixes breakage on Windows/ARM64 after D94355.

Modelled after the corresponding code for X86; not entirely familiar
with those aspects of that layer otherwise.

Differential Revision: https://reviews.llvm.org/D99572
2021-04-14 12:31:26 +03:00
Martin Storsjö 71c29b4cf3 [AArch64] Use '//' as comment string for MSVC assembly
As the actual MSVC toolset doesn't use the GAS-style assembly that
Clang/LLVM produces and consumes, there's no reference for what
string to use for e.g. comments when building with a MSVC triple.

This frees up the use of semicolon as separator string, just like
was done for GNU targets in 2341319564.
(Previously, both the separator and comment strings were set to
the same, a semicolon.)

Compiler-rt extensively uses separator chars in its assembly,
and that assembly should be buildable with clang-cl for MSVC too.

Differential Revision: https://reviews.llvm.org/D96259
2021-02-08 22:30:14 +02:00
Fangrui Song 66bcbdbc9c [AArch64InstPrinter] Change printADRPLabel to print the target address in hexadecimal form
Similar to D77853. Change ADRP to print the target address in hex, instead of the raw immediate.
The behavior is similar to GNU objdump but we also include `0x`.

Note: GNU objdump is not consistent whether or not to emit `0x` for different architectures. We try emitting 0x consistently for all targets.

```
GNU objdump:       adrp x16, 10000000
Old llvm-objdump:  adrp x16, #0
New llvm-objdump:  adrp x16, 0x10000000
```

`adrp Xd, 0x...` assembles to a relocation referencing `*ABS*+0x10000` which is not intended. We need to use a linker or use yaml2obj.
The main test is `test/tools/llvm-objdump/ELF/AArch64/pcrel-address.yaml`

Differential Revision: https://reviews.llvm.org/D93241
2020-12-16 09:20:55 -08:00
Fangrui Song ecd6d7254e [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html

Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option
A subsequent change will reject -long-option.
2020-03-15 17:46:23 -07:00
Martin Storsjo d0b5034b8a [COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355

llvm-svn: 331384
2018-05-02 18:24:37 +00:00
Martin Storsjo c61ff3bef1 [AArch64] Add support for secrel add/load/store relocations for COFF
Differential Revision: https://reviews.llvm.org/D43288

llvm-svn: 326480
2018-03-01 20:42:28 +00:00
Martin Storsjo 0b7bf7a2e3 [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations
In COFF, a symbol offset can't be stored in the relocation (as is
done in ELF or MachO), but is stored as the immediate in the
instruction itself. The immediate in the ADRP thus is the symbol
offset in bytes, not in pages. For the PAGEOFFSET_12A/L relocations,
ignore any offset outside of the lowest 12 bits; they won't have any
effect on the ADD/LDR/STR instruction itself but only on the associated
ADRP.

This is similar to how the same issue is handled for MOVW/MOVT
instructions in ELF (see e.g. SVN r307713, and r307728 in lld).

This fixes "fixup out of range" errors while building larger object
files, where temporary symbols end up as a plain section symbol and
an offset, and fixes any cases where the symbol offset mean that
the actual target ended up on a different page than the symbol
itself.

Differential Revision: https://reviews.llvm.org/D35791

llvm-svn: 309105
2017-07-26 11:19:17 +00:00
Martin Storsjo b2e9fcfca4 [AArch64] Force relocations for all ADRP instructions
This generalizes an existing fix from ELF to MachO and COFF.

Test that an ADRP to a local symbol whose offset is known at assembly
time still produces relocations, both for MachO and COFF. Test that
an ADRP without a @page modifier on MachO fails (previously it
didn't).

Differential Revision: https://reviews.llvm.org/D35544

llvm-svn: 308518
2017-07-19 20:14:32 +00:00
Mandeep Singh Grang a210f1d7bf [COFF, ARM64] Add initial relocation types
Reviewers: compnerd, ruiu, rnk

Reviewed By: compnerd

Subscribers: mstorsjo, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34857

llvm-svn: 308154
2017-07-17 00:05:32 +00:00