6f7072c66a
Added some eye-candy for Subtarget type checking
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Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
0ab01ff6e2
Small fixes for supporting dll* linkage types
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llvm-svn: 30441
2006-09-17 13:06:18 +00:00
d61d39ec53
Adding dllimport, dllexport and external weak linkage types.
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DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
llvm-svn: 30374
2006-09-14 18:23:27 +00:00
971e33930d
Turn X < 0 -> TEST X,X js
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llvm-svn: 30294
2006-09-13 17:04:54 +00:00
0c9ae46c5f
The sense of this branch was inverted :(
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llvm-svn: 30293
2006-09-13 16:56:12 +00:00
7a627676be
Compile X > -1 -> text X,X; js dest
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This implements CodeGen/X86/jump_sign.ll.
llvm-svn: 30283
2006-09-13 03:22:10 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
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llvm-svn: 30279
2006-09-12 21:04:05 +00:00
4259a0f654
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
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operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
11b0a5dbd4
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
89c5d04b9b
- Identify a vector_shuffle that can be turned into an undef, e.g.
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shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
llvm-svn: 30171
2006-09-08 01:50:06 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
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using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
162f2d5d4c
Revert this patch, the front-end has been fixed to make it unneccesary.
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llvm-svn: 29752
2006-08-17 18:43:24 +00:00
dfb3f0591d
'g' is handled by the front-end.
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llvm-svn: 29751
2006-08-17 18:12:28 +00:00
4a063c5ffb
Fix handling of 'g'. Closes 883
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llvm-svn: 29750
2006-08-17 17:50:12 +00:00
1c3210d08d
Add the 'c' constraint as needed by the linux kernel
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llvm-svn: 29747
2006-08-17 16:07:50 +00:00
fc60fb974c
Add support for S and D constraints, as needed to compile the linux kernel.
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llvm-svn: 29746
2006-08-17 15:35:43 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
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llvm-svn: 29614
2006-08-11 17:38:39 +00:00
bd1c5a8fb8
Match tablegen changes.
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llvm-svn: 29604
2006-08-11 09:08:15 +00:00
5c68bba085
Convert more calls of getNode() that takes a vector to pass in the start of an array.
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llvm-svn: 29601
2006-08-11 07:35:45 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
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in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
524129dd64
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
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The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
llvm-svn: 29420
2006-07-31 23:26:50 +00:00
9e56e5c003
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
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llvm-svn: 29307
2006-07-26 21:12:04 +00:00
74065bedf2
This opt is now handled in DAG combine.
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llvm-svn: 29243
2006-07-21 08:26:46 +00:00
4cf0238720
A splat of a vector constant of all zero or all one is the vector constant.
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llvm-svn: 29234
2006-07-20 23:09:47 +00:00
c8db10725b
Add information preventing several register class constraints from working.
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This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
llvm-svn: 29118
2006-07-12 16:59:49 +00:00
298ef37e02
Implement the inline asm 'A' constraint. This implements PR825 and
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CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
llvm-svn: 29101
2006-07-11 02:54:03 +00:00
79cf9a5342
Fixed stack objects do not specify alignments, but their offsets are known.
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Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
llvm-svn: 29090
2006-07-10 21:37:44 +00:00
9aabc1e16f
Mark internal function static
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llvm-svn: 29085
2006-07-10 19:53:12 +00:00
5987cfb7b1
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
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(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 08:33:52 +00:00
0261242aa6
Reorg. No functionality change.
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llvm-svn: 28999
2006-07-05 22:17:51 +00:00
38c5aee959
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
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llvm-svn: 28910
2006-06-24 08:36:10 +00:00
de7156f12c
Type of vector extract / insert index operand should be iPTR.
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llvm-svn: 28796
2006-06-15 08:14:54 +00:00
ca25486603
Add argument registers to the end of call operand list (partial fix).
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llvm-svn: 28783
2006-06-14 18:17:40 +00:00
0e14a56d35
Minor compilation speed improvement.
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llvm-svn: 28736
2006-06-09 06:24:42 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
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function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
2b2c1be49c
Typos
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llvm-svn: 28617
2006-06-01 05:53:27 +00:00
2489ccdd90
Remove a warning
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llvm-svn: 28607
2006-06-01 00:30:39 +00:00
550cb663e8
Remove dead code.
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llvm-svn: 28581
2006-05-31 00:50:42 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
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RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
b92f418408
Vector argument must be passed in memory location aligned on 16-byte boundary.
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llvm-svn: 28505
2006-05-26 20:37:47 +00:00
bfb5ea6875
Mac OS X ABI document lied. The first four XMM registers are used to pass
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vector arguments, not three.
llvm-svn: 28504
2006-05-26 19:22:06 +00:00
a01e799927
Minor update to make the code more clear
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llvm-svn: 28499
2006-05-26 18:39:59 +00:00
cbfb3d07e0
Update more comments.
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llvm-svn: 28498
2006-05-26 18:37:16 +00:00
763f9b00f0
Fix some comments.
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llvm-svn: 28497
2006-05-26 18:25:43 +00:00
83dc51d7ff
No need to handle illegal types.
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llvm-svn: 28496
2006-05-26 18:22:49 +00:00
8aca43e8da
Consistency
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llvm-svn: 28488
2006-05-25 23:31:23 +00:00
0421aca87a
Some clean up.
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llvm-svn: 28483
2006-05-25 22:38:31 +00:00
29f805ec65
Remove some dead code.
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llvm-svn: 28481
2006-05-25 22:25:52 +00:00
5ee96893ae
Build breakage.
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llvm-svn: 28475
2006-05-25 18:56:34 +00:00
2a33094284
Switch X86 over to a call-selection model where the lowering code creates
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the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
llvm-svn: 28463
2006-05-25 00:59:30 +00:00
Anton Korobeynikov