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Author SHA1 Message Date
Matt Arsenault 762d498808 AMDGPU: Add combine for trunc of bitcast from build_vector 
If the truncate is only accessing the first element of the vector,
we can use the original source value.

This helps with some combine ordering issues after operations are
lowered to integer operations between bitcasts of build_vector.
In particular it stops unnecessarily materializing the unused
top half of a vector in some cases.

llvm-svn: 331909
 2018-05-09 18:37:39 +00:00
Dmitry Preobrazhensky da4a7c01bf [AMDGPU][MC] Corrected GATHER4 opcodes 
See bug 36252: https://bugs.llvm.org/show_bug.cgi?id=36252

Differential Revision: https://reviews.llvm.org/D43874

Reviewers: artem.tamazov, arsenm
llvm-svn: 327278
 2018-03-12 15:03:34 +00:00
Changpeng Fang 4737e892de AMDGPU/SI: Add d16 support for image intrinsics. 
Summary:
  This patch implements d16 support for image load, image store and image sample intrinsics.

Reviewers:
  Matt, Brian.

Differential Revision:
  https://reviews.llvm.org/D3991

llvm-svn: 322903
 2018-01-18 22:08:53 +00:00