Commit Graph

67 Commits

Author SHA1 Message Date
Sean Callanan 050e0cdb9a Modified the Intel instruction tables to include
versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.

llvm-svn: 81818
2009-09-15 00:35:17 +00:00
Eric Christopher 9fe912de5f Implement sse4.2 string/text processing instructions:
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).

llvm-svn: 79377
2009-08-18 22:50:32 +00:00
Eric Christopher 7dfa9f2e56 Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508
2009-08-08 21:55:08 +00:00
Anton Korobeynikov 2589777f3f Add ability to override segment (mostly for code emitter purposes).
llvm-svn: 57380
2008-10-11 19:09:15 +00:00
Bill Wendling 76105a4a4f Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
SSE2 registers as well as the MMX registers.

llvm-svn: 55436
2008-08-27 21:32:04 +00:00
Bill Wendling 6cfd3830fb Nevermind. This broke the bootstrap (?!).
llvm-svn: 55318
2008-08-25 18:32:39 +00:00
Bill Wendling dd6759aea7 MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
instructions on having SSE2.

llvm-svn: 55317
2008-08-25 18:20:52 +00:00
Anton Korobeynikov 31099519d0 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
Is there way to avoid explicit target check?

llvm-svn: 55238
2008-08-23 15:53:19 +00:00
Dan Gohman a21bdda961 Fix comment spacing.
llvm-svn: 55047
2008-08-20 13:46:21 +00:00
Nate Begeman 55b7becb29 SSE codegen for vsetcc nodes
llvm-svn: 53719
2008-07-17 16:51:19 +00:00
Evan Cheng 96bdbd6c5d Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
Andrew Lenharth 0070dd1de3 Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
Nate Begeman 8ef50214f0 SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file

llvm-svn: 47035
2008-02-12 22:51:28 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng 01c7c198ee Fix JIT encoding for CMPSD as well.
llvm-svn: 45268
2007-12-20 19:57:09 +00:00
Chris Lattner dab6bd902e Fix the JIT encoding of cmp*ss, which aborts with this assertion currently:
X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'

I *think* this is right, but Evan, please verify.  It also looks like
CMPSDrr and maybe others are missing this info.  Evan, plz investigate.

llvm-svn: 45074
2007-12-16 20:12:41 +00:00
Evan Cheng 12c6be84ff Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
llvm-svn: 40628
2007-07-31 08:04:03 +00:00