llvm-project

Commit Graph

Author	SHA1	Message	Date
Vladimir Medic	643b398786	This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410	2013-07-30 10:12:14 +00:00
Akira Hatanaka	4d2ea3c696	[mips] Fix MipsAsmParser::parseCCRRegs. Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861	2013-07-22 19:30:38 +00:00
Vladimir Medic	3467b90786	This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch. llvm-svn: 186567	2013-07-18 09:28:35 +00:00
Jack Carter	2ad73da02b	Mips assembler: Explicit floating point condition register recognition. This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567	2013-04-15 22:21:55 +00:00
Nico Rieck	334c7bc7eb	Use object file specific section type for initial text section llvm-svn: 179494	2013-04-14 21:18:36 +00:00
Jack Carter	e948ec52d1	Adding support for instructions mfc0, mfc2, mtc0, mtc2 move from and to coprocessors 0 and 2. Contributer: Vladimir Medic llvm-svn: 165351	2012-10-06 01:17:37 +00:00
Jack Carter	a63b16ac1e	The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363	2012-09-07 00:23:42 +00:00

7 Commits