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13571 Commits

Author SHA1 Message Date
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Daniel Dunbar 86face8333 MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation. 
llvm-svn: 99249
 2010-03-23 03:13:05 +00:00
Daniel Dunbar a9ae3ae698 MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler. 
llvm-svn: 99248
 2010-03-23 02:36:58 +00:00
Daniel Dunbar e0c43577c1 MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation. 
llvm-svn: 99245
 2010-03-23 01:39:09 +00:00
Bob Wilson e60e3ab624 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson c286c88db0 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson 98bf5189d7 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson debe0bdb13 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen 5db5506093 Completely remove Blackfin patterns that thought JustCC was i1. 
Thanks, Chris!

llvm-svn: 99183
 2010-03-22 16:30:04 +00:00
Jeffrey Yasskin 7d116ce2e3 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
llvm-svn: 99182
 2010-03-22 16:13:21 +00:00
Daniel Dunbar fbd12cc36c MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC. 
llvm-svn: 99102
 2010-03-20 22:36:38 +00:00
Daniel Dunbar fed917e078 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
llvm-svn: 99097
 2010-03-20 22:36:22 +00:00
Bob Wilson 162242b63b pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!

llvm-svn: 99096
 2010-03-20 22:20:40 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson 59e5141d44 Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.

llvm-svn: 99094
 2010-03-20 21:57:36 +00:00
Bob Wilson b18adef4ad Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093
 2010-03-20 21:45:18 +00:00
Bob Wilson 89ba42c4ce Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090
 2010-03-20 21:15:48 +00:00
Bob Wilson 322cbff3d3 Add VST1 instructions with address register writeback. 
llvm-svn: 99083
 2010-03-20 20:54:36 +00:00
Bob Wilson 9152d96dfb Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.

llvm-svn: 99082
 2010-03-20 20:47:18 +00:00
Bob Wilson 9b1584245a Tidy some more comments and whitespace. 
llvm-svn: 99081
 2010-03-20 20:39:53 +00:00
Bob Wilson cf324658f6 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080
 2010-03-20 20:10:51 +00:00
Bob Wilson 7ee900da22 Tidy some comments and whitespace for consistency. 
llvm-svn: 99078
 2010-03-20 19:57:03 +00:00
Bob Wilson c0795f8b87 Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
 2010-03-20 18:35:24 +00:00
Bob Wilson d092669b48 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065
 2010-03-20 18:14:26 +00:00
Bob Wilson 496766cb56 Add VLD1 instructions with address register writeback. 
llvm-svn: 99062
 2010-03-20 17:59:03 +00:00
Benjamin Kramer 73fc06f60f PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*. 
llvm-svn: 99061
 2010-03-20 17:41:18 +00:00
Bob Wilson 2497d85c9e Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049
 2010-03-20 06:34:02 +00:00
Bob Wilson 614d1fdfc3 Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043
 2010-03-20 06:05:13 +00:00
Evan Cheng 3f6f769c4f If call result is in ST0 and it is not being passed to the caller's 
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.

llvm-svn: 99032
 2010-03-20 02:58:15 +00:00
Johnny Chen f833fad813 Add NLdStFrm Format. 
llvm-svn: 99014
 2010-03-20 00:17:00 +00:00
Johnny Chen 053e3510a3 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

llvm-svn: 99013
 2010-03-19 23:50:27 +00:00
Bob Wilson e4191e719b Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Chris Lattner 8352941b34 remove the patterns that I commented out in r98930, Dan verified 
that they are dead.

llvm-svn: 99000
 2010-03-19 21:43:36 +00:00
Kevin Enderby cf0843ed93 Fixed the encoding problems of the crc32 instructions. All had the Operand size 
override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980
 2010-03-19 20:04:42 +00:00
Daniel Dunbar c532697372 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
llvm-svn: 98972
 2010-03-19 18:07:48 +00:00
Johnny Chen 0dab68f3d0 Renumber LdStExFrm from 28 to 11 and shift the existing format values to make 
room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

llvm-svn: 98967
 2010-03-19 17:39:00 +00:00
Daniel Dunbar 4d7c8645fd MC: Add TargetAsmBackend::createObjectWriter. 
- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

llvm-svn: 98955
 2010-03-19 10:43:26 +00:00
Daniel Dunbar eaa367f5ae MCCodeEmitter: Add target independent fixup flag for is-pc-relative. 
llvm-svn: 98954
 2010-03-19 10:43:23 +00:00
Daniel Dunbar c5084cccc8 MC: Add TargetAsmBackend::isVirtualSection hook. 
llvm-svn: 98950
 2010-03-19 09:29:03 +00:00
Daniel Dunbar f0517efc6c MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task. 
llvm-svn: 98947
 2010-03-19 09:28:12 +00:00
Jeffrey Yasskin 22a411ff5b Remove a memory leak from the CBackend. 
llvm-svn: 98941
 2010-03-19 07:06:46 +00:00
Chris Lattner 0433699ef0 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.

llvm-svn: 98937
 2010-03-19 05:33:51 +00:00
Jeffrey Yasskin 4822dfcc9a Remove a memory leak from ThumbTargetMachine. 
llvm-svn: 98936
 2010-03-19 05:25:28 +00:00
Chris Lattner 83aeaab462 add a new SDNPVariadic SDNP node flag, and use it in 
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934
 2010-03-19 05:07:09 +00:00
Chris Lattner e5ac9382ce remove some damaged sign extend patterns that can never match. 
llvm-svn: 98932
 2010-03-19 04:53:47 +00:00
Chris Lattner 6d984166fc disable some illegal blackfin patterns. sext from i32 to i32 can never 
match.  Jakob, please take a look when you get a chance.

llvm-svn: 98931
 2010-03-19 04:53:21 +00:00
Chris Lattner 607795f917 comment out a bunch of parallel store patterns that apparently 
can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930
 2010-03-19 04:14:21 +00:00
Daniel Dunbar 857955243e Fix -Asserts warnings. 
llvm-svn: 98928
 2010-03-19 03:18:23 +00:00