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Author SHA1 Message Date
Stanislav Mekhanoshin dad7cf62de [AMDGPU] computeKnownBitsForTargetNode for 24 bit mul 
Differential Revision: https://reviews.llvm.org/D37168

llvm-svn: 311896
 2017-08-28 16:35:37 +00:00
Stanislav Mekhanoshin 5fa289f0d8 [AMDGPU] Narrow lshl from 64 to 32 bit if possible 
Turn expensive 64 bit shift into 32 bit if shift does not overflow int:
shl (ext x) => zext (shl x)

Differential Revision: https://reviews.llvm.org/D33367

llvm-svn: 303569
 2017-05-22 16:58:10 +00:00