Commit Graph

580 Commits

Author SHA1 Message Date
Brian Gaeke 8351d8c1a8 make -print-machineinstrs work for both SparcV9 and X86
llvm-svn: 12122
2004-03-04 19:16:23 +00:00
Alkis Evlogimenos b9501c1f8c Add assertion for scale verification.
llvm-svn: 12120
2004-03-04 18:05:02 +00:00
Misha Brukman a6025e6480 Doxygenify some comments.
llvm-svn: 12064
2004-03-01 23:53:11 +00:00
Brian Gaeke 427cec1395 TargetCacheInfo has been removed; its only uses were to propagate a constant
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

llvm-svn: 12043
2004-03-01 06:43:29 +00:00
Chris Lattner 1f4642c47c Handle passing constant integers to functions much more efficiently. Instead
of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.

llvm-svn: 12028
2004-03-01 02:42:43 +00:00
Chris Lattner 5c7d3cda78 Fix a minor code-quality issue. When passing 8 and 16-bit integer constants
to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!

llvm-svn: 12026
2004-03-01 02:34:08 +00:00
Alkis Evlogimenos 9a4653edfa Add instruction name description.
llvm-svn: 11998
2004-02-29 18:44:03 +00:00
Alkis Evlogimenos 0824ffc697 Use correct template for SHLD and SHRD instructions so that the memory
operand size is correctly specified.

llvm-svn: 11997
2004-02-29 09:19:40 +00:00
Alkis Evlogimenos c7fd0770a0 Improve allocation order:
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996
2004-02-29 09:17:01 +00:00
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
2004-02-29 08:50:03 +00:00
Chris Lattner 1e36fb030c Eliminate the X86-specific BMI functions, using BuildMI instead.
Replace uses of addZImm with addImm.

llvm-svn: 11992
2004-02-29 07:22:16 +00:00
Chris Lattner 9a97573267 Fix a miscompilation of 197.parser that occurs when you have single basic
block loops.

llvm-svn: 11990
2004-02-29 07:10:16 +00:00
Chris Lattner ed01da8f0b Adjust to change in TII ctor arguments
llvm-svn: 11987
2004-02-29 06:31:44 +00:00
Chris Lattner ca89812db7 These two virtual methods are never called.
llvm-svn: 11984
2004-02-29 05:59:33 +00:00
Alkis Evlogimenos 876f6f96d0 Use correct template for ADC instruction with memory operands.
llvm-svn: 11974
2004-02-29 02:18:17 +00:00
Alkis Evlogimenos fa63580517 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
to denote this fact.

llvm-svn: 11972
2004-02-28 23:46:44 +00:00
Alkis Evlogimenos 4953ae085a Floating point loads/stores act on memory operands. Rename them to
denote this fact.

llvm-svn: 11971
2004-02-28 23:42:35 +00:00
Alkis Evlogimenos c6948fa762 Rename instruction templates to be easier to the human eye to
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
2004-02-28 23:09:03 +00:00
Alkis Evlogimenos 5b5dee4afb Uncomment instructions that take both an immediate and a memory
operand but their sizes differ.

llvm-svn: 11969
2004-02-28 22:06:59 +00:00
Alkis Evlogimenos 194939086d Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
2004-02-28 22:02:05 +00:00
Alkis Evlogimenos 2debead504 Do not generate instructions with mismatched memory/immediate sized
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
2004-02-28 06:01:43 +00:00
Alkis Evlogimenos 24b3d0bdae Further comment updates.
llvm-svn: 11933
2004-02-28 03:20:31 +00:00
Alkis Evlogimenos f87966b8c4 Update comments.
llvm-svn: 11932
2004-02-28 03:12:31 +00:00
Alkis Evlogimenos 2dbc79df84 My previous commit broke the jit. The shift instructions always take
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
2004-02-28 02:56:26 +00:00
Alkis Evlogimenos b10b04c5ec Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
instructions.

llvm-svn: 11923
2004-02-27 19:46:30 +00:00
Alkis Evlogimenos 75ed0f67bf Fix encoding of ADD and SUB family of instructions. Also rearrange
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
2004-02-27 18:57:00 +00:00
Alkis Evlogimenos 58270fcf1f Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
llvm-svn: 11921
2004-02-27 18:55:12 +00:00
Alkis Evlogimenos 9476b7cbe5 Add memory operand folding support for the SETcc family of
instructions.

llvm-svn: 11907
2004-02-27 16:13:37 +00:00
Alkis Evlogimenos 8d99063b38 Add memory operand folding support for SHLD and SHRD instructions.
llvm-svn: 11905
2004-02-27 15:03:18 +00:00
Alkis Evlogimenos 3537404299 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
llvm-svn: 11903
2004-02-27 09:28:43 +00:00
Alkis Evlogimenos f020dfb43c Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
2004-02-27 06:57:05 +00:00
Alkis Evlogimenos 61719d48d2 Uncomment assertions that register# != 0 on calls to
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.

llvm-svn: 11882
2004-02-26 22:00:20 +00:00
Chris Lattner 9192bbdad9 Fix some warnings, some of which were spurious, and some of which were real
bugs.  Thanks Brian!

llvm-svn: 11859
2004-02-26 01:20:02 +00:00
Chris Lattner 64c9b223bd Fix failures in 099.go due to the cfgsimplify pass creating switch instructions
where there did not used to be any before

llvm-svn: 11829
2004-02-25 19:30:19 +00:00
Chris Lattner 309327a4b5 Teach the instruction selector how to transform 'array' GEP computations into X86
scaled indexes.  This allows us to compile GEP's like this:

int* %test([10 x { int, { int } }]* %X, int %Idx) {
        %Idx = cast int %Idx to long
        %X = getelementptr [10 x { int, { int } }]* %X, long 0, long %Idx, ubyte 1, ubyte 0
        ret int* %X
}

Into a single address computation:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        lea %EAX, DWORD PTR [%EAX + 8*%ECX + 4]
        ret

Before it generated:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        shl %ECX, 3
        add %EAX, %ECX
        lea %EAX, DWORD PTR [%EAX + 4]
        ret

This is useful for things like int/float/double arrays, as the indexing can be folded into
the loads&stores, reducing register pressure and decreasing the pressure on the decode unit.
With these changes, I expect our performance on 256.bzip2 and gzip to improve a lot.  On
bzip2 for example, we go from this:

10665 asm-printer           - Number of machine instrs printed
   40 ra-local              - Number of loads/stores folded into instructions
 1708 ra-local              - Number of loads added
 1532 ra-local              - Number of stores added
 1354 twoaddressinstruction - Number of instructions added
 1354 twoaddressinstruction - Number of two-address instructions
 2794 x86-peephole          - Number of peephole optimization performed

to this:
9873 asm-printer           - Number of machine instrs printed
  41 ra-local              - Number of loads/stores folded into instructions
1710 ra-local              - Number of loads added
1521 ra-local              - Number of stores added
 789 twoaddressinstruction - Number of instructions added
 789 twoaddressinstruction - Number of two-address instructions
2142 x86-peephole          - Number of peephole optimization performed

... and these types of instructions are often in tight loops.

Linear scan is also helped, but not as much.  It goes from:

8787 asm-printer           - Number of machine instrs printed
2389 liveintervals         - Number of identity moves eliminated after coalescing
2288 liveintervals         - Number of interval joins performed
3522 liveintervals         - Number of intervals after coalescing
5810 liveintervals         - Number of original intervals
 700 spiller               - Number of loads added
 487 spiller               - Number of stores added
 303 spiller               - Number of register spills
1354 twoaddressinstruction - Number of instructions added
1354 twoaddressinstruction - Number of two-address instructions
 363 x86-peephole          - Number of peephole optimization performed

to:

7982 asm-printer           - Number of machine instrs printed
1759 liveintervals         - Number of identity moves eliminated after coalescing
1658 liveintervals         - Number of interval joins performed
3282 liveintervals         - Number of intervals after coalescing
4940 liveintervals         - Number of original intervals
 635 spiller               - Number of loads added
 452 spiller               - Number of stores added
 288 spiller               - Number of register spills
 789 twoaddressinstruction - Number of instructions added
 789 twoaddressinstruction - Number of two-address instructions
 258 x86-peephole          - Number of peephole optimization performed

Though I'm not complaining about the drop in the number of intervals.  :)

llvm-svn: 11820
2004-02-25 07:00:55 +00:00
Chris Lattner d1ee55d439 * Make the previous patch more efficient by not allocating a temporary MachineInstr
to do analysis.

*** FOLD getelementptr instructions into loads and stores when possible,
    making use of some of the crazy X86 addressing modes.

For example, the following C++ program fragment:

struct complex {
    double re, im;
    complex(double r, double i) : re(r), im(i) {}
};
inline complex operator+(const complex& a, const complex& b) {
    return complex(a.re+b.re, a.im+b.im);
}
complex addone(const complex& arg) {
    return arg + complex(1,0);
}

Used to be compiled to:
_Z6addoneRK7complex:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
***     mov %EDX, %ECX
        fld QWORD PTR [%EDX]
        fld1
        faddp %ST(1)
***     add %ECX, 8
        fld QWORD PTR [%ECX]
        fldz
        faddp %ST(1)
***     mov %ECX, %EAX
        fxch %ST(1)
        fstp QWORD PTR [%ECX]
***     add %EAX, 8
        fstp QWORD PTR [%EAX]
        ret

Now it is compiled to:
_Z6addoneRK7complex:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        fld QWORD PTR [%ECX]
        fld1
        faddp %ST(1)
        fld QWORD PTR [%ECX + 8]
        fldz
        faddp %ST(1)
        fxch %ST(1)
        fstp QWORD PTR [%EAX]
        fstp QWORD PTR [%EAX + 8]
        ret

Other programs should see similar improvements, across the board.  Note that
in addition to reducing instruction count, this also reduces register pressure
a lot, always a good thing on X86.  :)

llvm-svn: 11819
2004-02-25 06:13:04 +00:00
Chris Lattner 4b3514c173 Add a helper to create an addressing mode given all of the pieces.
llvm-svn: 11818
2004-02-25 06:01:07 +00:00
Chris Lattner d825d30f42 add an inefficient way of folding structure and constant array indexes together
into a single LEA instruction.  This should improve the code generated for
things like X->A.B.C[12].D.

The bigger benefit is still coming though.  Note that this uses an LEA instruction
instead of an add, giving the register allocator more freedom.  We should probably
never generate ADDri32's.

llvm-svn: 11817
2004-02-25 03:45:50 +00:00
Chris Lattner f85e33cd79 Implement special case for storing an immediate into memory so that we don't need
an intermediate register.

llvm-svn: 11816
2004-02-25 02:56:58 +00:00
Alkis Evlogimenos af2de4848e Refactor rewinding code for finding the first terminator of a basic
block into MachineBasicBlock::getFirstTerminator().

This also fixes a bug in the implementation of the above in both
RegAllocLocal and InstrSched, where instructions where added after the
terminator if the basic block's only instruction was a terminator (it
shouldn't matter for RegAllocLocal since this case never occurs in
practice).

llvm-svn: 11748
2004-02-23 18:14:48 +00:00
Chris Lattner cb185a34bb Simplify code a bit, don't go off the end of the block, now that the current
block we are in might be empty

llvm-svn: 11744
2004-02-23 07:42:19 +00:00
Chris Lattner 4ffd4443ce We were forgetting to add FP_REG_KILL instructions to basic blocks which will
eventually get an assignment due to elimination of PHIs.

llvm-svn: 11743
2004-02-23 07:29:45 +00:00
Chris Lattner abb9162999 Work around a gas bug. Print '-9223372036854775808' as unsigned.
llvm-svn: 11729
2004-02-23 03:27:05 +00:00
Chris Lattner 7e90628a8a Implement cast fp -> bool
llvm-svn: 11728
2004-02-23 03:21:41 +00:00
Chris Lattner 6590c29971 Stop passing iterators around by reference now that we have ilists!
Implement cast Type::ULongTy -> double

llvm-svn: 11726
2004-02-23 03:10:10 +00:00
Chris Lattner 378157c3d7 Add a new cmove instruction
llvm-svn: 11722
2004-02-23 01:16:05 +00:00
Chris Lattner cdd56634b0 Only insert FP_REG_KILL instructions in MachineBasicBlocks that actually
use FP instructions.  This reduces the number of instructions inserted in
176.gcc (for example) from 58074 to 101 (it doesn't use much FP, which
is typical).  This reduction speeds up the entire code generator.  In the
case of 176.gcc, llc went from taking 31.38s to 24.78s.  The passes that
sped up the most are the register allocator and the 2 live variable analysis
passes, which sped up 2.3, 1.3, and 1.5s respectively.  The asmprinter
pass also sped up because it doesn't print the instructions in comments :)

Note that this patch is likely to expose latent bugs in machine code passes,
because now basicblock can be empty, where they were never empty before.  I
cleaned out regalloclocal, but who knows about linscan :)

llvm-svn: 11717
2004-02-22 19:47:26 +00:00
Alkis Evlogimenos 8358cc573d Move MOTy::UseType enum into MachineOperand. This eliminates the
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715
2004-02-22 19:23:26 +00:00
Chris Lattner fae7564027 Reduce the number of pointless copies inserted due to constant pointer refs.
Also, make an assertion actually fireable!

llvm-svn: 11713
2004-02-22 17:35:42 +00:00
Chris Lattner fa3ebd6ad5 Fix bug in previous checkout: leave the iterator at the first instruction
AFTER the GEP that was emitted.  :(

llvm-svn: 11712
2004-02-22 17:05:38 +00:00