Commit Graph

18027 Commits

Author SHA1 Message Date
Akira Hatanaka ca88b4abec Prevent generation of redundant addiu instructions that compute address of
static variables or functions. 

llvm-svn: 133803
2011-06-24 17:55:19 +00:00
Justin Holewinski 7d65756aba PTX: Re-work target sm/compute selection and add some basic GPU
targets: g80, gt200, gf100(fermi)

llvm-svn: 133799
2011-06-24 16:27:49 +00:00
Rafael Espindola cff9c5e9a0 Fix CellSPU CMakeList.txt.
llvm-svn: 133792
2011-06-24 13:58:45 +00:00
Evan Cheng 8e731166d0 Fix CellSPU CMakeLists.txt
llvm-svn: 133787
2011-06-24 05:04:48 +00:00
Evan Cheng 247533179a Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
2011-06-24 01:44:41 +00:00
Eli Friedman 5c958bb528 Add support for movntil/movntiq mnemonics. Reported on llvmdev.
llvm-svn: 133759
2011-06-23 21:07:47 +00:00
Evan Cheng 8b2a2a1158 Rename TargetOptions::StackAlignment to StackAlignmentOverride.
llvm-svn: 133739
2011-06-23 18:15:47 +00:00
Evan Cheng 1b049f5851 Remove TargetOptions.h dependency from ARMSubtarget.
llvm-svn: 133738
2011-06-23 18:15:17 +00:00
Justin Holewinski 6cdd72a9ca PTX: Always use registers for return values, but use .param space for device
parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

llvm-svn: 133736
2011-06-23 18:10:13 +00:00
Justin Holewinski 90b336ba0c PTX: Whitespace fixes and remove commented out code
llvm-svn: 133734
2011-06-23 18:10:07 +00:00
Justin Holewinski 9b459d9d7b PTX: Prevent DCE from eliminating st.param calls, and unify the handling of
st.param and ld.param

FIXME: Test cases still need to be updated
llvm-svn: 133733
2011-06-23 18:10:05 +00:00
Justin Holewinski 9472541ba1 PTX: Use .param space for parameters in device functions for SM >= 2.0
FIXME: DCE is eliminating the final st.param.x calls, figure out why
llvm-svn: 133732
2011-06-23 18:10:03 +00:00
Evan Cheng 3a0c5e52ff Remove TargetOptions.h dependency from X86Subtarget.
llvm-svn: 133726
2011-06-23 17:54:54 +00:00
Dylan Noblesmith f490726633 CppBackend: fixup for api change
This broke after r133364.

llvm-svn: 133709
2011-06-23 12:11:37 +00:00
Jay Foad 61ea0e4692 Reinstate r133513 (reverted in r133700) with an additional fix for a
-Wshorten-64-to-32 warning in Instructions.h.

llvm-svn: 133708
2011-06-23 09:09:15 +00:00
Eric Christopher 96513120b7 Revert r133513:
"Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512)."

Due to some additional warnings.

llvm-svn: 133700
2011-06-23 06:24:52 +00:00
Bill Wendling 9af2fa9d1b Use the presence of the __compact_unwind section to indicate that a target
supports compact unwind info instead of having a separate flag indicating this.

llvm-svn: 133685
2011-06-23 05:13:28 +00:00
Evan Cheng ee9b90a727 Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment.
llvm-svn: 133679
2011-06-23 01:53:43 +00:00
Bill Wendling f942585dae Add a flag that indicates whether a target supports compact unwind info or not.
llvm-svn: 133662
2011-06-22 23:16:51 +00:00
Bill Wendling d346304373 Add a __LD,__compact_unwind section.
If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.

llvm-svn: 133658
2011-06-22 22:22:24 +00:00
Jim Grosbach 51897047da Add missing header.
llvm-svn: 133640
2011-06-22 20:40:30 +00:00
Jim Grosbach 2354f87a9d Move ARMMachObjectWriter to its own file.
Just tidy up a bit. No functional change.

llvm-svn: 133638
2011-06-22 20:14:52 +00:00
Justin Holewinski 08d0f3550a PTX: Fix FrameIndex mapping bug
llvm-svn: 133619
2011-06-22 16:07:03 +00:00
Dan Bailey 55ec2a8929 Test Commit.
llvm-svn: 133613
2011-06-22 09:04:30 +00:00
Justin Holewinski 6fafebfb6a PTX: Add signed integer comparisons
llvm-svn: 133599
2011-06-22 02:09:50 +00:00
Justin Holewinski 54e3c0f5d9 PTX: Add .address_size directive if PTX version >= 2.3
Patch by Wei-Ren Chen

llvm-svn: 133589
2011-06-22 00:43:56 +00:00
Nick Lewycky ef9c497e4c Add support for assembling "movq" when it's correct to do so, while continuing
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.

llvm-svn: 133565
2011-06-21 22:45:41 +00:00
Eric Christopher e256cd0565 Handle the memory-ness of all U+ ARM constraints.
Noticed on inspection.

llvm-svn: 133553
2011-06-21 22:10:57 +00:00
Evan Cheng 8d971ad5b7 Reorg. No functionality change.
llvm-svn: 133533
2011-06-21 19:00:54 +00:00
Bob Wilson 646dd0f4d1 Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

llvm-svn: 133524
2011-06-21 17:35:13 +00:00
Anna Zaks 083f0b5a7e Add support for sadd.with.overflow and uadd.with.overflow intrinsics to the CBackend by emitting definitions for each intrinsic that occurs in the module.
llvm-svn: 133522
2011-06-21 17:18:15 +00:00
Jay Foad a97a2c998e Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512).

llvm-svn: 133513
2011-06-21 10:33:19 +00:00
Evan Cheng 4c0bd9629d Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

llvm-svn: 133503
2011-06-21 06:01:08 +00:00
Chad Rosier 184f3b37e2 Revert r133435 and r133449 to appease buildbots.
llvm-svn: 133499
2011-06-21 02:09:03 +00:00
Akira Hatanaka 27029885f0 Add A0 and A1 to the list of registers used for returning a value in order to
handle functions with return type Complex long long.

llvm-svn: 133497
2011-06-21 01:28:11 +00:00
Akira Hatanaka 5b350be79d Coding style fixes.
llvm-svn: 133496
2011-06-21 01:02:03 +00:00
Akira Hatanaka 4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777.
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
Justin Holewinski cd4484d25d PTX: Fix conversion between predicates and value types
llvm-svn: 133454
2011-06-20 18:42:48 +00:00
Nick Lewycky c7df192279 Emit movq for 64-bit register to XMM register moves, but continue to accept
movd when assembling.

llvm-svn: 133452
2011-06-20 18:33:26 +00:00
Justin Holewinski e8ae1db4d8 PTX: Fix if-then-else formatting and add missing asserts
llvm-svn: 133447
2011-06-20 17:08:56 +00:00
Justin Holewinski c7b073da0f PTX: Add basic register spilling code
The current implementation generates stack loads/stores, which are
really just mov instructions from/to "special" registers.  This may
not be the most efficient implementation, compared to an approach where
the stack registers are directly folded into instructions, but this is
easier to implement and I have yet to see a case where ptxas is unable
to see through this kind of register usage and know what is really
going on.

llvm-svn: 133443
2011-06-20 15:56:20 +00:00
Roman Divacky 254f82112d Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflow
with 32bit values.

llvm-svn: 133439
2011-06-20 15:28:39 +00:00
Jay Foad e03c05c35a Change how PHINodes store their operands.
Change PHINodes to store simple pointers to their incoming basic blocks,
instead of full-blown Uses.

Note that this loses an optimization in SplitCriticalEdge(), because we
can no longer walk the use list of a BasicBlock to find phi nodes. See
the comment I removed starting "However, the foreach loop is slow for
blocks with lots of predecessors".

Extend replaceAllUsesWith() on a BasicBlock to also update any phi
nodes in the block's successors. This mimics what would have happened
when PHINodes were proper Users of their incoming blocks. (Note that
this only works if OldBB->replaceAllUsesWith(NewBB) is called when
OldBB still has a terminator instruction, so it still has some
successors.)

llvm-svn: 133435
2011-06-20 14:38:01 +00:00
Jay Foad 372ad64b4d Make better use of the PHINode API.
Change various bits of code to make better use of the existing PHINode
API, to insulate them from forthcoming changes in how PHINodes store
their operands.

llvm-svn: 133434
2011-06-20 14:18:48 +00:00
Jay Foad 6002068c13 Fix a FIXME by making GlobalVariable::getInitializer() return a
const Constant *.

llvm-svn: 133400
2011-06-19 18:37:11 +00:00
Benjamin Kramer 25e17b0f89 Remove unused but set variables.
llvm-svn: 133347
2011-06-18 11:09:41 +00:00
Jakob Stoklund Olesen b68fee1e82 Delete unneeded allocation order override.
llvm-svn: 133331
2011-06-18 02:30:02 +00:00
Jakob Stoklund Olesen 831ae0105a Switch ARM to using AltOrders instead of MethodBodies.
This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326
2011-06-18 01:14:46 +00:00
Jakob Stoklund Olesen 3337f7d50a Switch x86 to using AltOrders instead of MethodBodies.
llvm-svn: 133325
2011-06-18 01:14:43 +00:00
Jakob Stoklund Olesen 19d968e62f Reserve D16-D13 on subtargets that don't support them.
llvm-svn: 133321
2011-06-18 00:53:27 +00:00