Commit Graph

411933 Commits

Author SHA1 Message Date
Nikita Popov 81d35f27dd [DebugInstrRef] Memoize variable order during sorting (NFC)
Instead of constructing DebugVariables and looking up the order
in the comparison function, compute the order upfront and then sort
a vector of (order, instr).

This improves compile-time by -0.4% geomean on CTMark ReleaseLTO-g.

Differential Revision: https://reviews.llvm.org/D117575
2022-01-20 16:04:24 +01:00
Simon Pilgrim 4130357f96 [X86] Fix v16f32 ADDSUB test
This was supposed to ensure we're not generating 512-bit ADDSUB nodes, but cut+paste typos meant we weren't generating a full 512-bit pattern
2022-01-20 14:58:36 +00:00
eopXD 14c5fd920b [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction
According to v-spec v1.0, `zve-32x` is the new minimum extension to include
to have vector instructions.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D112613
2022-01-20 06:53:48 -08:00
Jan Svoboda 9011903e36 [llvm][vfs] Abstract in-memory node creation
The creation of in-memory VFS nodes happens in a single function that deduces what kind of node to create from the arguments. This leads to complicated if-then-else logic that's difficult to cleanly extend.

This patch abstracts away in-memory node creation via a type-erased factory function that's passed instead.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D117648
2022-01-20 15:48:02 +01:00
Jan Svoboda 9e24d14ac8 [llvm][vfs] NFC: Virtualize in-memory `getStatus`
This patch virtualizes the `getStatus` function on `InMemoryNode` in LLVM VFS. Currently, this is implemented via top-level function `getNodeStatus` that tries to cast `InMemoryNode *` into each subtype. Virtual functions seem to be the simpler solution here.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D117649
2022-01-20 15:48:02 +01:00
Stephan Herhut 6d45284618 [mlir][memref] Add better support for identity layouts in memref.collapse_shape canonicalizer
When computing the new type of a collapse_shape operation, we need to at least
take into account whether the type has an identity layout, in which case we can
easily support dynamic strides. Otherwise, the canonicalizer creates invalid
IR.

Longer term, both the verifier and the canoncializer need to be extended to
support the general case.

Differential Revision: https://reviews.llvm.org/D117772
2022-01-20 15:31:43 +01:00
Stanislav Gatev c95cb4de1b [clang][dataflow] Intersect ExprToLoc when joining environments
This is part of the implementation of the dataflow analysis framework.
See "[RFC] A dataflow analysis framework for Clang AST" on cfe-dev.

Reviewed-by: xazax.hun

Differential Revision: https://reviews.llvm.org/D117754
2022-01-20 14:30:17 +00:00
Valentin Clement 010a10b738
[flang][NFC] Remove extra braces
Noticed during the upstreaming process.
2022-01-20 15:18:59 +01:00
Mubashar Ahmad 35737df4dc [Clang][AArch64][ARM] Unaligned Access Warning Added
Added warning for potential cases of
unaligned access when option
-mno-unaligned-access has been specified

Differential Revision: https://reviews.llvm.org/D116221
2022-01-20 14:12:49 +00:00
Nikita Popov 60147c6034 [EarlyCSE] Regenerate test checks (NFC) 2022-01-20 14:49:26 +01:00
Florian Hahn 67aa314bce
[IRGen] Do not overwrite existing attributes in CGCall.
When adding new attributes, existing attributes are dropped. While
this appears to be a longstanding issue, this was highlighted by D105169
which dropped a lot of attributes due to adding the new noundef
attribute.

Ahmed Bougacha (@ab) tracked down the issue and provided the fix in
CGCall.cpp. I bundled it up and updated the tests.
2022-01-20 13:45:19 +00:00
Simon Tatham a4ac40e92f [AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.

Reviewed By: labrinea

Differential Revision: https://reviews.llvm.org/D117755
2022-01-20 13:37:58 +00:00
Simon Tatham 19b9cd4eae [MC] Add a disassembly test for Armv8-R sysregs.
This is the counterpart to llvm/test/MC/AArch64/armv8r-sysreg.s,
checking all the same encodings when fed to the disassembler.
2022-01-20 13:37:58 +00:00
Abinav Puthan Purayil d8b690409d [AMDGPU] Set MemoryVT for truncstores in tblgen.
GlobalISelEmitter was skipping these patterns when its predicates were
checked. This patch should allow us to select d16_hi stores in
GlobalISel.

Differential Revision: https://reviews.llvm.org/D117762
2022-01-20 19:05:12 +05:30
Marek Kurdej 69ecd2484f [clang-format] Indicate source location on test failure. NFC. 2022-01-20 14:10:59 +01:00
Simon Pilgrim 304cfc706a [X86] combineConcatVectorOps - remove superfluous Subtarget.hasAVX() check
This function only ever gets called by AVX targets, and we already assert for this at the top of the function
2022-01-20 12:56:09 +00:00
Simon Pilgrim c4f5fd76da [X86] combineConcatVectorOps - add handling for X86ISD::VSHL/VSRL/VSRA
These can be handled the same as the vector shift by immediate variants that are already handled.
2022-01-20 12:56:08 +00:00
Jay Foad 847bb26820 [AMDGPU] Regenerate some MIR checks 2022-01-20 12:41:40 +00:00
Valentin Clement ccaaeca910
[flang][NFC] Move current inliner files in Dialect directory
This patch just move the files from the Transforms directory to
the Dialect directory.

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D117661
2022-01-20 13:34:44 +01:00
Valentin Clement 911c137054
[flang][NFC] Cleanup dependent dialects and make def homogenous
Remove unnecessary dependent dialect and make the definition of the
pass more homogenous with the two others.

This patch is part of the upstreaming effort from fir-dev branch.

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D117688
2022-01-20 13:33:56 +01:00
Fraser Cormack ca36cc56ac [RISCV] Match RVV VF variants also through masked operations
This brings floating-point RVV vector/scalar support more in line with
the integer vector patterns, which can already match '.vx' instructions
with masked operations.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117697
2022-01-20 12:08:02 +00:00
Peter Waller d4a6bf4d1a Revert "[AArch64][SVE][VLS] Move extends into arguments of comparisons"
This reverts commit db04d3e30b, which
causes a buildbot failure.
2022-01-20 12:01:23 +00:00
Fraser Cormack 5a12024b95 [RISCV] Optimize lowering of floating-point -0.0
This idea has come up in several reviews -- D115978 and D105902 -- so I
can't take any credit for the idea. Instead of using a constant pool to
lower -0.0, we can emit a sequence of two instructions:

    fmv.[hwd].x freg, zero
    fsgnjn.[hsd] freg, freg, freg

This is only done when the floating-point type is legal.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117687
2022-01-20 11:46:28 +00:00
Prashant Kumar 770353cd94 [MLIR] The return type in the `computeSingleVarRepr` function is modified to include equality expressions.
Earlier `computeSingleVarRepr` was returning a pair of upper bound and
lower bound indices of the inequality contraints that can be expressed
as a floordiv of an affine function. The equality expression can also be
expressed as a floordiv but contains only one index and hence the `LocalRepr`
class is introduced to facilitate this.

Reviewed By: Groverkss

Differential Revision: https://reviews.llvm.org/D117430
2022-01-20 16:40:58 +05:30
David Spickett 787f91b0bb [lldb] Remove non-address bits from addresses given to memory tag commands
Although the memory tag commands use a memory tag manager to handle
addresses, that only removes the top byte.

That top byte is 4 bits of memory tag and 4 free bits, which is more
than it should strictly remove but that's how it is for now.

There are other non-address bit uses like pointer authentication.
To ensure the memory tag manager only has to deal with memory tags,
use the ABI plugin to remove the rest.

The tag access test has been updated to sign all the relevant pointers
and require that we're running on a system with pointer authentication
in addition to memory tagging.

The pointers will look like:
<4 bit user tag><4 bit memory tag><signature><bit virtual address>

Note that there is currently no API for reading memory tags. It will
also have to consider this when it arrives.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D117672
2022-01-20 10:48:14 +00:00
David Spickett 585abe3ba5 [lldb] Rename MemoryTagManager RemoveNonAddressBits to RemoveTagBits
This better describes the intent of the method. Which for AArch64
is removing the top byte which includes the memory tags.

It does not include pointer signatures, for those we need to use
the ABI plugin. The rename makes this a little more clear.

It's a bit awkward that the memory tag manager is removing the whole
top byte not just the memory tags but it's an improvement for now.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D117671
2022-01-20 10:47:05 +00:00
Florian Hahn 782c0dd1a1
[IRBuilder] Migrate and-folding to value-based FoldAnd.
Similar to the migration of or-folding to FoldOr, there are a few cases
where the fold in IRBuilder::CreateAnd triggered directly. Those have
been updated.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D117431
2022-01-20 10:22:21 +00:00
Valentin Clement 90efbe697a
[flang][NFC] Fix header guard and comment 2022-01-20 10:56:23 +01:00
Casey Carter 67d483aba2 [libcxx][test] Use TEST_HAS_BUILTIN in test code
... rather than using `__has_builtin` directly. This both (1) allows a compiler that doesn't speak `__has_builtin` to workaround with preprocessor magic, and (2) avoids diagnostics about things that look like function like macros after `#if` but are not.
2022-01-20 01:47:29 -08:00
eopXD 60b6e73769 [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap
Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. This makes
clang_cc1 fail to imply into `zve32x` for the vector extension, and test
cases will have to add ` -target-feature +experimental-zve32x` in order
to work.

This patch fixes it.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D113336
2022-01-20 01:47:10 -08:00
Valentin Clement 96ca6d312c
[flang][NFC] Fix header guard
Fix header guard to fit other files.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D117662
2022-01-20 10:24:07 +01:00
Matthias Springer 7a1579ac67 [mlir][bufferization] Move one-shot bufferization to Bufferization dialect
This commit is the first step towards unifying core bufferization and One-Shot Bufferize.

This commit does not move over the implementations of BufferizableOpInterface yet. This will be done in separate commits. This change does also not move the unit tests yet. The tests will be moved together with op interface implementations and split into separate files.

Differential Revision: https://reviews.llvm.org/D117641
2022-01-20 18:21:20 +09:00
David Spickett 6732c43897 [llvm][AArch64] Accept armv8.8 "hbc" and "mops" in .arch_extension directive
Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D117693
2022-01-20 09:16:08 +00:00
Victor Perez c10c748878 [LegalizeTypes][VP] Add widening support for vp.gather and vp.scatter
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117557
2022-01-20 08:57:57 +00:00
Marek Kurdej 794b1eebe7 [clang-format] Add tests for aligning `operator=` with `=delete`. NFC.
Also, add test case from https://github.com/llvm/llvm-project/issues/33044.
This was actually fixed in 480a1fab72, but there were no tests for delete.
2022-01-20 09:39:08 +01:00
Nikita Popov 0d20407d1a Reapply [MemCpyOpt] Look through pointer casts when checking capture
This is a recommit of the patch without changes. The reason for
the revert has been addressed in D117679.

-----

The user scanning loop above looks through pointer casts, so we
also need to strip pointer casts in the capture check. Previously
the source was incorrectly considered not captured if a bitcast
was passed to the call.
2022-01-20 09:30:21 +01:00
Nikita Popov 655a7024db Reapply [MemCpyOpt] Make capture check during call slot optimization more precise
This is a recommit of the patch without changes. The reason for
the revert has been addressed in D117679.

-----

Call slot optimization is currently supposed to be prevented if
the call can capture the source pointer. Due to an implementation
bug, this check currently doesn't trigger if a bitcast of the source
pointer is passed instead. I'm somewhat afraid of the fallout of
fixing this bug (due to heavy reliance on call slot optimization
in rust), so I'd like to strengthen the capture reasoning a bit first.

In particular, I believe that the capture is fine as long as a)
the call itself cannot depend on the pointer identity, because
neither dest has been captured before/at nor src before the
call and b) there is no potential use of the captured pointer
before the lifetime of the source alloca ends, either due to
lifetime.end or a return from a function. At that point the
potentially captured pointer becomes dangling.

Differential Revision: https://reviews.llvm.org/D115615
2022-01-20 09:30:20 +01:00
Richard baa08d1ec3 [clang-tidy] Revert documentation change (NFC)
Restore a fix to the list of checks that was undone by a recent commit.
2022-01-20 01:27:23 -07:00
Chenbing.Zheng 0be3da1fab [RISCV] Add intrinsic for Zbt extension
RV32: fsl, fsr, fsri
RV64: fsl, fsr, fsri, fslw, fsrw, fsriw

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117468
2022-01-20 08:27:05 +00:00
Nikita Popov d7bff2e9d2 [MemCpyOpt] Fix metadata merging during call slot optimization
Call slot optimization currently merges the metadata between the
call and the load. However, we also need to merge in the metadata
of the store.

Part of the reason why we might have gotten away with this
previously is that usually the load and the store are the same
instruction (a memcpy), this can only happen if call slot
optimization occurs on an actual load/store pair.

This addresses the issue reported in
https://reviews.llvm.org/D115615#3251386.

Differential Revision: https://reviews.llvm.org/D117679
2022-01-20 09:25:13 +01:00
Nikita Popov 22ee510dac [Support] Remove incorrect noalias return attribute in BumpPtrAllocator
The memory returned by the Allocate() function is also otherwise
accessible -- and is indeed accessed by the DestroyAll() method of
SpecificBumpPtrAlloactor. This is a violation of the noalias return
contract.

This should address the issue reported in
https://reviews.llvm.org/D116728#3252464.

Differential Revision: https://reviews.llvm.org/D117664
2022-01-20 09:17:35 +01:00
Jez Ng 8f811effac [lld-macho] Fix grammar in doc 2022-01-19 23:59:35 -08:00
Jino Park 560eb2277b [clang-format] Fix bug in parsing `operator<` with template
Fixes https://github.com/llvm/llvm-project/issues/44601.

This patch handles a bug when parsing a below example code :

```
template <class> class S;

template <class T> bool operator<(S<T> const &x, S<T> const &y) {
  return x.i < y.i;
}

template <class T> class S {
  int i = 42;
  friend bool operator< <>(S const &, S const &);
};

int main() { return S<int>{} < S<int>{}; }
```
which parse `< <>` as `<< >`, not `< <>` in terms of tokens as discussed in discord.

1. Add a condition in `tryMergeLessLess()` considering `operator` keyword and `>`
2. Force to leave a whitespace between `tok::less` and a template opener
3. Add unit test

Reviewed By: MyDeveloperDay, curdeius

Differential Revision: https://reviews.llvm.org/D117398
2022-01-20 08:59:04 +01:00
eopXD 8eae99dfe5 [RISCV] Add the zve extension according to the v1.0 spec
`zve` is the new standard vector extension to specify varying degrees of
vector support for embedding processors. The `zve` extension is related
to the `zvl` extension and other updates that are added in v1.0.

According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro `__riscv_v_max_elen`,  `__riscv_v_max_elen_fp` for
`zve` and it can be used by applications that uses the vector extension.

Authored by: Zakk Chen <zakk.chen@sifive.com> @khchen
Co-Authored by: Eop Chen <eop.chen@sifive.com> @eopXD

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D112408
2022-01-19 23:48:28 -08:00
Lang Hames d5ae7a99d1 [ORC] Fix another missing std::move from 9eb4939b86. 2022-01-20 17:58:37 +11:00
Lang Hames f8752e28fd [ORC] Fix missing std::move from 9eb4939b86. 2022-01-20 17:56:56 +11:00
Lang Hames 9eb4939b86 [ORC] Allow JITDylib::getDFSLinkOrder and friends to fail for defunct JITDylibs.
Calls to JITDylib's getDFSLinkOrder and getReverseDFSLinkOrder methods (both
static an non-static versions) are now valid to make on defunct JITDylibs, but
will return an error if any JITDylib in the link order is defunct.

This means that platforms can safely lookup link orders by name in response to
jit-dlopen calls from the ORC runtime, even if the call names a defunct
JITDylib -- the call will just fail with an error.
2022-01-20 17:45:32 +11:00
Fangrui Song a7a4115bf3 [ELF] Replace .zdebug string comparison with SHF_COMPRESSED check. NFC 2022-01-19 22:33:32 -08:00
Jonas Devlieghere 10ea731699 [dsymutil] Don't print timestamp warning if we have no timestamp
If we have no timestamp (0), don't print the corresponding warning. The
binary holder already successfully ignores these cases, but the warning
for swift interface files was lacking it.

rdar://86036385

Differential revision: https://reviews.llvm.org/D117333
2022-01-19 21:51:58 -08:00
Johannes Doerfert 6f2ee1ca5e [OpenMP][AMDGPU] Optimize the linked in math libraries
Once we linked in math files, potentially even if we link in only other
"system libraries", we want to optimize the code again. This is not only
reasonable but also helps to hide various problems with the missing
attribute annotations in the math libraries.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D116906
2022-01-19 23:36:36 -06:00