be1bb0f8b1
PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
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instructions.
llvm-svn: 73009
2009-06-07 01:07:55 +00:00
8d6d4b9289
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
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PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
llvm-svn: 70225
2009-04-27 18:41:29 +00:00
b93db668b3
Revert 69952. Causes testsuite failures on linux x86-64.
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llvm-svn: 69967
2009-04-24 12:40:33 +00:00
bb881d66f4
PR2957
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ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
2009-04-24 03:42:54 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
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llvm-svn: 55504
2008-08-28 21:40:38 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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llvm-svn: 48380
2008-03-15 00:03:38 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
e20f380fbf
remove some isStore flags that are now inferred automatically.
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llvm-svn: 45652
2008-01-06 05:53:26 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
b9bf812ba5
Add the 64-bit versions of the DS* Altivec instructions.
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llvm-svn: 41717
2007-09-05 04:05:20 +00:00
f5124b36e4
Fix arguments for some Altivec instructions. From SWB.
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llvm-svn: 40957
2007-08-09 00:49:19 +00:00
4e7ff3593c
Fix spelling of mtvscr and mfvscr.
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llvm-svn: 40908
2007-08-07 23:08:00 +00:00
581d2795dc
Vector fneg must be expanded into fsub -0.0, X.
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llvm-svn: 40586
2007-07-30 07:51:22 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
8091f28d1a
fix incorrect encoding of vminsw.
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llvm-svn: 34351
2007-02-16 21:20:09 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
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llvm-svn: 29174
2006-07-18 16:33:26 +00:00
868a75bec6
Remove some now-unneeded casts from instruction patterns. With the casts
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removed, tblgen produces identical output to with them in.
llvm-svn: 28867
2006-06-20 00:39:56 +00:00
99d3da9d2c
Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.
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llvm-svn: 27908
2006-04-20 19:01:30 +00:00
0cd0065c58
Make sure that the new instructions selected have the right type. This fixes
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CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
llvm-svn: 27868
2006-04-20 05:58:10 +00:00
06a21ba96b
Implement a TODO: have the legalizer canonicalize a bunch of operations to
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one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
llvm-svn: 27731
2006-04-16 01:37:57 +00:00
873202fabd
Add patterns for matching vnots with bit converted inputs. Most of these will
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go away when I start using evan's binop type canonicalizer
llvm-svn: 27725
2006-04-15 23:45:24 +00:00
74cf9ff761
Rename get_VSPLI_elt -> get_VSPLTI_elt
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Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
llvm-svn: 27614
2006-04-12 17:37:20 +00:00
e318a7574e
Ensure that zero vectors are always v4i32, which forces them to CSE with
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each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
llvm-svn: 27609
2006-04-12 16:53:28 +00:00
d71a1f946d
Change the interface to the predicate that determines if vsplti* can be used.
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No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
a4bbfaed5c
Match vpku[hw]um(x,x).
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Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
f38e033270
Add support for matching vmrg(x,x) patterns
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llvm-svn: 27463
2006-04-06 22:02:42 +00:00
d1dcb52093
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
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llvm-svn: 27457
2006-04-06 21:11:54 +00:00
1d33819194
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
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lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
e8b83b4206
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
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vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
c94d932447
Add all of the data stream intrinsics and instructions. woo
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llvm-svn: 27442
2006-04-05 22:27:14 +00:00
39dc64c955
Fix a typo
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llvm-svn: 27440
2006-04-05 20:15:25 +00:00
2f8e2b2895
add vsl
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llvm-svn: 27425
2006-04-05 01:16:22 +00:00
575352ac20
add vmladduhm
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llvm-svn: 27423
2006-04-05 00:49:48 +00:00
5a528e565b
Add m[tf]vscr instructions.
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llvm-svn: 27421
2006-04-05 00:03:57 +00:00
281bb5da1d
Add missing byte merges.
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llvm-svn: 27418
2006-04-04 23:43:56 +00:00
fc50ae521c
Add FP -> Int Conversions
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llvm-svn: 27417
2006-04-04 23:25:02 +00:00
96338b6a21
add average intrinsics
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llvm-svn: 27416
2006-04-04 23:14:00 +00:00
95c7adc7cb
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
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handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
b1e6d84544
Plug in the byte and short splats
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llvm-svn: 27387
2006-04-04 00:05:13 +00:00
9ccd61c893
Add the full set of min/max instructions
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llvm-svn: 27372
2006-04-03 15:58:28 +00:00
dc72c17798
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
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llvm-svn: 27331
2006-04-01 22:41:47 +00:00
ff77dc0a08
Shrinkify some more intrinsic definitions.
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llvm-svn: 27322
2006-03-31 22:41:56 +00:00
20d3f3726f
Pull operand asm string into base class, shrinkifying intrinsic definitions.
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No functionality change.
llvm-svn: 27320
2006-03-31 22:34:05 +00:00
110fc74b97
Fix 80 column violations :)
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llvm-svn: 27315
2006-03-31 21:57:36 +00:00
a4150f751d
fix a pasto
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llvm-svn: 27308
2006-03-31 21:19:06 +00:00
e7fd4b0274
Add vperm support for all datatypes
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llvm-svn: 27307
2006-03-31 20:00:35 +00:00
070181c927
compactify some more instruction definitions
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llvm-svn: 27288
2006-03-31 05:38:32 +00:00
45c709388a
Compactify comparisons.
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llvm-svn: 27287
2006-03-31 05:32:57 +00:00
Eli Friedman