6 Commits

Author	SHA1	Message	Date
Luis Marques	3d0fbafd0b	[RISCV] Switch to the Machine Scheduler ... Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106	2019-09-17 11:15:35 +00:00
Luis Marques	2d550d19b3	Revert Patch from Phabricator ... This reverts r372092 (git commit e38695a025) llvm-svn: 372104	2019-09-17 10:52:09 +00:00
Luis Marques	e38695a025	Patch from Phabricator ... llvm-svn: 372092	2019-09-17 09:43:08 +00:00
Alex Bradbury	5dabe03b41	[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV ... r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493	2019-05-23 12:43:13 +00:00
Alex Bradbury	bd1c56648f	[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068 ... rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to reflect this, and remove the NOLIB check lines (they're redundant given that the RV32I and RV64I check lines generated by update_llc_test_checks.py already demonstrate there is no libcall). llvm-svn: 356074	2019-03-13 18:25:23 +00:00
Ana Pazos	9a3dc3e60b	[LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types ... Summary: Except for custom floating point types x86_fp80 and ppc_fp128, expand Y = FNEG(X) to Y = X ^ sign mask to avoid library call. Using bitwise operation can improve code size and performance. Reviewers: efriedma Reviewed By: efriedma Subscribers: efriedma, kpn, arsenm, eli.friedman, javed.absar, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D57875 llvm-svn: 353757	2019-02-11 22:10:08 +00:00