ad98f1671d
[ARM] Introduce the 'sevl' instruction in ARMv8.
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This also removes the restriction on the immediate field of the 'hint'
instruction.
llvm-svn: 191744
2013-10-01 12:39:11 +00:00
43cb13a5c9
ARM: ISB cannot be passed the same options as DMB
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ISB should only accepts full system sync, other options are reserved
llvm-svn: 183656
2013-06-10 14:17:08 +00:00
631df63e54
ARM: fix CPS decoding when ambiguous with QADD
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Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.
Add some necessary safe guards in CPS decoding as well.
llvm-svn: 183610
2013-06-08 13:38:52 +00:00
0e9892fe3a
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
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According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
llvm-svn: 183307
2013-06-05 13:23:51 +00:00
dc1764c5a4
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
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llvm-svn: 181705
2013-05-13 14:10:04 +00:00
27ff504653
ARM: Permit "sp" in ARM variant of STREXD instructions
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Patch from Mihail Popa
llvm-svn: 179854
2013-04-19 15:44:32 +00:00
a155ab2dd2
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
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llvm-svn: 179847
2013-04-19 09:58:09 +00:00
c6047655a7
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
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These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
llvm-svn: 179171
2013-04-10 12:08:35 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
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llvm-svn: 161161
2012-08-02 08:21:27 +00:00
10dd40e42d
Fix #13241 , a bug around shift immediate operand for ARM instruction ADR.
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llvm-svn: 161159
2012-08-02 08:13:13 +00:00
8a8e9d1b63
Specify cpu to unbreak tests.
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llvm-svn: 155604
2012-04-26 01:38:10 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
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llvm-svn: 142624
2011-10-20 22:01:48 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00
ed6d3e813e
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
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llvm-svn: 137495
2011-08-12 19:42:45 +00:00
Joey Gouly