pointer to the annotated struct type can be used as an
Objective-C object pointer. If an argument is given, the
type is actually "toll-free bridged" to the specific type
named there, rather than just to 'id'.
For now, we cannot rely on all types being so annotated,
and we'll always have to have exceptions for things like
CFTypeRef (aka const void*), but this is clearly a good
foundation for improving toolage in this area.
llvm-svn: 140779
- This fixes a host of obscure bugs with regards to how warning mapping options composed with one another, and I believe makes the code substantially easier to read and reason about.
llvm-svn: 140770
- No actual functionality change for now, we still also use the diag::Mapping::{MAP_WARNING_NO_ERROR,MAP_ERROR_NO_FATAL,MAP_WARNING_SHOW_IN_SYSTEM_HEADER} for a little while longer.
llvm-svn: 140768
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
it enables the hardware watchpoint for all existing threads. Add a test file for that.
Also fix MachThreadList::DisableHardwareWatchpoint().
llvm-svn: 140757
- The TextDiagnosticPrinter code is still fragile as it is just "reverse engineering" what the diagnostic engine is doing. Not my current priority to fix though.
llvm-svn: 140752
DiagnosticsEngine::setDiagnosticGroup{ErrorAsFatal,WarningAsError} methods which
more accurately model the correct API -- no internal change to the diagnostics
engine yet though.
- Also, stop honoring -Werror=everything (etc.) as a valid (but oddly behaved) option.
llvm-svn: 140747
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
llvm-svn: 140744
we have the ability to create a new, distict diagnostic consumer when
we go off and build a module. This avoids the currently horribleness
where the same diagnostic consumer sees diagnostics for multiple
translation units (and multiple SourceManagers!) causing all sorts of havok.
llvm-svn: 140743
Duncan Sands