3 Commits

Author	SHA1	Message	Date
Craig Topper	86e604c4d6	[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates. ... SimplifyDemandedBits can remove set bits from immediates from instructions like AND/OR/XOR. This can prevent them from being efficiently codegened on RISCV. This adds an initial version that tries to keep or form 12 bit sign extended immediates for AND operations to enable use of ANDI. If that doesn't work we'll try to create a 32 bit sign extended immediate to use LUI+ADDIW. More optimizations are possible for different size immediates or different operations. But this is a good starting point that already has test coverage. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94628	2021-01-15 11:14:14 -08:00
Michael Munday	e28b6a60bc	[RISCV][NFC] Regenerate RISCV CodeGen tests ... Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841	2020-12-09 19:42:49 +00:00
Hsiangkai Wang	f7bc7c2981	[RISCV] Support Zfh half-precision floating-point extension. ... Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex Differential Revision: https://reviews.llvm.org/D90738	2020-12-03 09:16:33 +08:00