35b2f75733
Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
...
llvm-svn: 211254
2014-06-19 06:10:58 +00:00
a0050b0961
R600/SI: Add intrinsics for various math instructions.
...
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.
llvm-svn: 211247
2014-06-19 01:19:19 +00:00
2b0fa433a0
Use stdint macros for specifying size of constants
...
llvm-svn: 211231
2014-06-18 22:11:03 +00:00
692bd5ec2f
R600: Handle fnearbyint
...
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.
llvm-svn: 211229
2014-06-18 22:03:45 +00:00
51b8e7b2e7
R600/SI: add gather4 and getlod intrinsics (v3)
...
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.
Reviewed-by: Tom Stellard
llvm-svn: 211228
2014-06-18 22:00:29 +00:00
b55c68f171
Use LL suffix for literal that should be 64-bits.
...
This hopefully fixes Windows
llvm-svn: 211225
2014-06-18 21:40:43 +00:00
85f0dbce5c
R600: Expand vector fceil
...
Move fp64 fceil tests to fceil64.ll
v2: rebase
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
2014-06-18 17:57:29 +00:00
d22626f6bb
Work around ridiculous warning.
...
Apparently C++ doesn't really have hex floating point constants.
llvm-svn: 211192
2014-06-18 17:45:58 +00:00
43160e7af2
R600/SI: Add intrinsics for brev instructions
...
llvm-svn: 211187
2014-06-18 17:13:57 +00:00
dbc9aae1fb
R600/SI: Prettier operand printing for 64-bit ops.
...
Copy what is done for 32-bit already so the order is about the same.
llvm-svn: 211186
2014-06-18 17:13:51 +00:00
4601093267
R600: Implement f64 ftrunc, ffloor and fceil.
...
CI has instructions for these, so this fixes them for older hardware.
llvm-svn: 211183
2014-06-18 17:05:30 +00:00
e8208ec95b
R600: Custom lower f64 frint for pre-CI
...
llvm-svn: 211182
2014-06-18 17:05:26 +00:00
7aeb813b2a
R600/SI: Temporary fix for f64 fneg
...
This should be a source modifier, but this unblocks
most of my math patches.
llvm-svn: 211181
2014-06-18 17:05:22 +00:00
520e7c44c1
R600/SI: Comparisons set vcc.
...
llvm-svn: 211178
2014-06-18 16:53:48 +00:00
ecf5133a2b
R600: Implement 64bit SRA
...
v2: Use capitalized variable name
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211159
2014-06-18 12:27:17 +00:00
900ff2e74b
R600: Implement 64bit SRL
...
v2: use C++ style comment
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211158
2014-06-18 12:27:15 +00:00
25f362766e
R600: Implement 64bit SHL
...
v2: Use c++ style comment
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211157
2014-06-18 12:27:13 +00:00
092f332ef2
R600/SI: Make sure target flags are set on pseudo VOP3 instructions
...
llvm-svn: 211120
2014-06-17 19:34:46 +00:00
295b86e81d
R600/SI: Match cttz_zero_undef
...
llvm-svn: 211116
2014-06-17 17:36:27 +00:00
8579601050
R600/SI: Match ctlz_zero_undef
...
llvm-svn: 211115
2014-06-17 17:36:24 +00:00
880a80ad07
R600: Use LDS and vectors for private memory
...
llvm-svn: 211110
2014-06-17 16:53:14 +00:00
85ad429f1f
R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
...
llvm-svn: 211109
2014-06-17 16:53:09 +00:00
aad4659470
SelectionDAG: Expand i64 = FP_TO_SINT i32
...
llvm-svn: 211108
2014-06-17 16:53:07 +00:00
8942276a2a
R600/SI: Re-initialize the m0 register after using it for indirect addressing
...
We need to store a value greater than or equal to the number of LDS
bytes allocated by the shader in the m0 register in order for LDS
instructions to work correctly.
We always initialize m0 at the beginning of a shader, but this register
is also used for indirect addressing offsets, so we need to
re-initialize it any time we use indirect addressing.
llvm-svn: 211107
2014-06-17 16:53:04 +00:00
2a60de548a
Fix copy paste error
...
llvm-svn: 211003
2014-06-15 21:22:52 +00:00
717c1d0319
R600: Remove a few more things from AMDILISelLowering
...
Try to keep all the setOperationActions for integer ops
together.
llvm-svn: 211001
2014-06-15 21:08:58 +00:00
b5dff9ab50
R600: Fix assert on vector sdiv
...
llvm-svn: 211000
2014-06-15 21:08:54 +00:00
14d4645e46
R600: Move / cleanup more leftover AMDIL stuff.
...
llvm-svn: 210998
2014-06-15 20:23:38 +00:00
1578aa78d4
R600: Move division custom lowering out of AMDILISelLowering
...
llvm-svn: 210997
2014-06-15 20:08:02 +00:00
cf9a9a148e
R600: Report that integer division is expensive.
...
Divides by weird constants now emit much better code.
llvm-svn: 210995
2014-06-15 19:48:16 +00:00
66ee0816da
R600: Remove dead code
...
llvm-svn: 210994
2014-06-15 19:48:13 +00:00
b2e8744eeb
Fix typo
...
llvm-svn: 210968
2014-06-14 04:26:07 +00:00
e682a19a1c
R600: Fix asserts related to constant initializers
...
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.
An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.
llvm-svn: 210967
2014-06-14 04:26:05 +00:00
41aa27c96b
R600: Use address space enum instead of value
...
llvm-svn: 210966
2014-06-14 04:26:01 +00:00
fd8c24ede8
R600: Cleanup some old AMDIL stuff.
...
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.
No functionality change.
llvm-svn: 210922
2014-06-13 17:20:53 +00:00
bc5b5370de
R600: Remove AMDIL instruction and register definitions
...
Most of these are no longer used any more.
llvm-svn: 210915
2014-06-13 16:38:59 +00:00
c02eea7f64
R600: Don't call setOperationAction with things that aren't opcodes.
...
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.
llvm-svn: 210888
2014-06-13 07:44:38 +00:00
825fb0b094
R600/SI: Fix selection error on i64 rotl / rotr.
...
Evergreen is still broken due to missing shl_parts.
llvm-svn: 210885
2014-06-13 04:00:30 +00:00
2e59a45f80
R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
...
llvm-svn: 210869
2014-06-13 01:32:00 +00:00
d881e9195a
R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
...
llvm-svn: 210868
2014-06-13 01:31:56 +00:00
bfd480d79f
R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
...
llvm-svn: 210865
2014-06-13 01:02:57 +00:00
5d47d4ac7e
R600: Mostly remove remaining AMDIL intrinsics.
...
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.
llvm-svn: 210827
2014-06-12 21:15:44 +00:00
2c81994f92
R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
...
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.
llvm-svn: 210756
2014-06-12 08:21:54 +00:00
4a9cea608c
R600: Set correct InstrItinClass for instructions using *Helper classes
...
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.
This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.
llvm-svn: 210703
2014-06-11 20:51:42 +00:00
3fe21f8afa
R600: BCNT_INT is a vector only instruction
...
llvm-svn: 210702
2014-06-11 20:51:39 +00:00
2acc7a4570
R600/SI: Fix bitcast between v2i32 and f64
...
This is the same problem fixed in r210664 for more types.
The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.
llvm-svn: 210692
2014-06-11 19:31:13 +00:00
845438204f
R600/SI: Update place using old subtarget predicate
...
llvm-svn: 210683
2014-06-11 18:11:34 +00:00
caa0ec2851
R600/SI: Add common 64-bit LDS atomics
...
llvm-svn: 210680
2014-06-11 18:08:54 +00:00
1f10c5e2c9
R600/SI: Add instruction definitions for 64-bit LDS atomics
...
llvm-svn: 210679
2014-06-11 18:08:50 +00:00
c793e1d9dc
R600/SI: Add 32-bit LDS atomic cmpxchg
...
llvm-svn: 210678
2014-06-11 18:08:48 +00:00
9e874541ac
R600/SI: Use LDS atomic inc / dec
...
llvm-svn: 210677
2014-06-11 18:08:45 +00:00
0e69e8128c
R600/SI: Add other LDS atomic operations
...
llvm-svn: 210676
2014-06-11 18:08:42 +00:00
8c6613d2bf
R600/SI: Add instruction definitions for more LDS ops
...
llvm-svn: 210675
2014-06-11 18:08:39 +00:00
7ddcd83d49
R600/SI: Fix backwards names for local atomic instructions.
...
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.
llvm-svn: 210674
2014-06-11 18:08:37 +00:00
725741004c
R600/SI: Refactor local atomics.
...
Use patterns that will also match the immediate offset to
match the normal read / writes.
llvm-svn: 210673
2014-06-11 18:08:34 +00:00
364a6747aa
R600/SI: Use v_cvt_f32_ubyte* instructions
...
This eliminates extra extract instructions when loading an i8 vector to
a float vector.
llvm-svn: 210666
2014-06-11 17:50:44 +00:00
064c206d23
R600/SI: Fix selection failure on scalar_to_vector
...
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.
Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.
llvm-svn: 210664
2014-06-11 17:40:32 +00:00
ace0080a4a
Try to fix the msvc build.
...
llvm-svn: 210636
2014-06-11 04:41:37 +00:00
10da3b2516
Use cast instead of assert + dyn_cast
...
llvm-svn: 210628
2014-06-11 03:30:06 +00:00
c9df794042
R600: Add helper functions.
...
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.
llvm-svn: 210627
2014-06-11 03:29:54 +00:00
4e07b1d76b
R600/SI: Emit an error when attempting to spill VGPRs v4
...
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.
v2:
- Fix build
v3:
- Added crash fix when spilling SPGRs
v4:
- Use V_MOV_B32 as a dummy instruction instead of S_NOP
Patch by: Darren Powell
https://bugs.freedesktop.org/show_bug.cgi?id=75276
llvm-svn: 210588
2014-06-10 21:20:41 +00:00
060ae39022
R600/SI: Fix a crash when spilling SGPRs
...
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.
This fixes a crash in the game Antichamber.
https://bugs.freedesktop.org/show_bug.cgi?id=75276
llvm-svn: 210587
2014-06-10 21:20:38 +00:00
6042506b5c
R600: Use BCNT_INT for evergreen
...
llvm-svn: 210569
2014-06-10 19:18:28 +00:00
8333e4378e
R600/SI: Implement i64 ctpop
...
llvm-svn: 210568
2014-06-10 19:18:24 +00:00
b5b5110b5c
R600/SI: Use bcnt instruction for ctpop
...
llvm-svn: 210567
2014-06-10 19:18:21 +00:00
6e43965fbc
R600: Handle fcopysign
...
llvm-svn: 210564
2014-06-10 19:00:20 +00:00
b2cbf799d1
R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
...
llvm-svn: 210563
2014-06-10 18:54:59 +00:00
3ca1bfc728
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
...
This consolidates code from the Hexagon, R600, and XCore targets.
No functionality change intended.
llvm-svn: 210539
2014-06-10 16:01:22 +00:00
93840c095a
R600/SI: Rename VOP3 helper class to be more general
...
It has other uses besides shift instructions.
llvm-svn: 210478
2014-06-09 17:00:46 +00:00
689f325099
R600/SI: Keep 64-bit not on SALU
...
llvm-svn: 210476
2014-06-09 16:36:31 +00:00
13ccc8f1bc
R600: Fix selection failure for vector bswap
...
llvm-svn: 210475
2014-06-09 16:20:25 +00:00
151304691c
R600/SI: Match rsq instructions
...
llvm-svn: 210226
2014-06-05 00:15:55 +00:00
c6f338dd5e
Use nullptr
...
llvm-svn: 210222
2014-06-05 00:01:12 +00:00
08d84943af
Fix typos
...
llvm-svn: 210135
2014-06-03 23:06:13 +00:00
616a8e42b1
R600: Set all float vector expands in the same place
...
llvm-svn: 209988
2014-06-01 07:38:21 +00:00
b9e1eec363
R600/SI: Remove redundant patterns
...
These patterns are already handled in the instruction definition.
llvm-svn: 209979
2014-05-31 19:25:17 +00:00
aeca2fa9f7
R600/SI: Fix [s|u]int_to_fp for i1
...
llvm-svn: 209971
2014-05-31 06:47:42 +00:00
b5c4835502
R600/SI: Fix pattern variable names.
...
These are confusing enough since the order swaps,
so give them more useful names.
llvm-svn: 209787
2014-05-29 01:18:01 +00:00
46b51b7f62
R600: Add definition for flat address space ID.
...
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.
llvm-svn: 209463
2014-05-22 18:27:07 +00:00
05e96f4444
R600: Try to convert BFE back to standard bit ops when possible.
...
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.
llvm-svn: 209462
2014-05-22 18:09:12 +00:00
5565f65e13
R600: Add dag combine for BFE
...
llvm-svn: 209461
2014-05-22 18:09:07 +00:00
bf8694d36d
R600: Implement ComputeNumSignBitsForTargetNode for BFE
...
llvm-svn: 209460
2014-05-22 18:09:03 +00:00
af6df9d943
R600: Implement computeMaskedBitsForTargetNode for BFE
...
llvm-svn: 209459
2014-05-22 18:09:00 +00:00
493c5f1bc4
R600: Expand mul24 for GPUs without it
...
llvm-svn: 209458
2014-05-22 18:00:24 +00:00
f15a05623e
R600: Expand mad24 for GPUs without it
...
llvm-svn: 209457
2014-05-22 18:00:20 +00:00
eb260206c3
R600: Add intrinsics for mad24
...
llvm-svn: 209456
2014-05-22 18:00:15 +00:00
f37abc71de
R600/SI: Move instruction pattern to instruction definition
...
llvm-svn: 209454
2014-05-22 17:45:20 +00:00
c3a73c3087
R600/SI: Match fp_to_uint / uint_to_fp for f64
...
llvm-svn: 209388
2014-05-22 03:20:30 +00:00
40100887b6
R600: Add comment describing problems with LowerConstantInitializer
...
llvm-svn: 209333
2014-05-21 22:59:17 +00:00
6a57fd8b47
R600: Partially fix constant initializers for structs and vectors.
...
This should extend the current workaround to work with structs
that only contain legal, scalar types.
llvm-svn: 209331
2014-05-21 22:42:42 +00:00
03df7eeda1
Use cast<> instead of unchecked dyn_cast
...
llvm-svn: 209310
2014-05-21 18:03:59 +00:00
0a3b8f5507
Remove unused method declaration
...
llvm-svn: 209174
2014-05-19 22:55:35 +00:00
0dfed533ec
Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.
...
llvm-svn: 209126
2014-05-19 14:29:04 +00:00
c721a23882
R600/SI: Refactor the VOP3_32 tablegen class
...
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.
llvm-svn: 209028
2014-05-16 20:56:47 +00:00
0e70de57a3
R600/SI: Add a PredicateControl class for managing TableGen predicates
...
This was inspired by the PredicateControl class in the MIPS backend.
llvm-svn: 209027
2014-05-16 20:56:45 +00:00
0289ff4a4f
R600/SI: Move tablegen patterns away from instruction defs
...
llvm-svn: 209026
2014-05-16 20:56:44 +00:00
2671338497
R600/SI: Remove unused instruction
...
llvm-svn: 209025
2014-05-16 20:56:43 +00:00
f719ee9e76
R600/SI: Promote f32 SELECT to i32
...
llvm-svn: 209024
2014-05-16 20:56:41 +00:00
725db5d2c8
R600/SI: Remove duplicate pattern
...
llvm-svn: 209023
2014-05-16 20:56:37 +00:00
d504a74e3c
Use range for
...
llvm-svn: 208922
2014-05-15 21:44:05 +00:00
Craig Topper