f0bfc6a675
Fix how livein live intervals are handled. Previously it could end at MBB start. Sorry, no small test case possible.
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llvm-svn: 66129
2009-03-05 03:34:26 +00:00
b3783639cb
Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register.
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llvm-svn: 64082
2009-02-08 11:04:35 +00:00
76a2736c74
Exit with nice warnings when register allocator run out of registers.
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llvm-svn: 63267
2009-01-29 02:20:59 +00:00
c544cb0eca
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
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llvm-svn: 62600
2009-01-20 19:12:24 +00:00
f6768bd9cb
The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away:
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v1024 = EDI // not killed
=
= EDI
One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.
This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.
llvm-svn: 61847
2009-01-07 02:08:57 +00:00
0869f78555
Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this.
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172 %ECX<def> = MOV32rr %reg1039<kill>
180 INLINEASM <es:subl $5,$1
sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
188 %EAX<def> = MOV32rr %EAX<kill>
196 %ECX<def> = MOV32rr %ECX<kill>
204 %ECX<def> = MOV32rr %ECX<kill>
212 %EAX<def> = MOV32rr %EAX<kill>
220 %EAX<def> = MOV32rr %EAX
228 %reg1039<def> = MOV32rr %ECX<kill>
The early clobber operand ties ECX input to the ECX def.
The live interval of ECX is represented as this:
%reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
The right way to represent this is something like
%reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47)
Of course that won't work since that means overlapping live ranges defined by two val#.
The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom.
llvm-svn: 61259
2008-12-19 20:58:01 +00:00
9de2ac8e8b
Clarify some comments.
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llvm-svn: 60683
2008-12-08 04:53:23 +00:00
43c0891838
Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.
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llvm-svn: 60596
2008-12-05 17:41:31 +00:00
994faaf218
Fix comment.
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llvm-svn: 60592
2008-12-05 17:00:16 +00:00
d24be45d99
Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
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llvm-svn: 60586
2008-12-05 05:45:42 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
3336b1f06b
LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs code
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and the LiveInterval.h top-level comment and accordingly. This fixes blocks
having spurious live-in registers in boundary cases.
llvm-svn: 60092
2008-11-26 05:50:31 +00:00
cb181bb203
Silence unused variable warnings.
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llvm-svn: 59841
2008-11-21 20:00:59 +00:00
8fed4ce0b8
Use find_first/find_next to iterate through all the set bits in a
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BitVector, instead of manually testing each bit.
llvm-svn: 59246
2008-11-13 16:31:27 +00:00
5efcb61337
Remove some debugging code made redundant by the change to do
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coalescing as a separate pass rather than inside of
LiveIntervalAnalysis.
llvm-svn: 59146
2008-11-12 17:09:23 +00:00
938e201528
- Rewrite code that update register live interval that's split.
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- Create and update spill slot live intervals.
- Lots of bug fixes.
llvm-svn: 58367
2008-10-29 05:06:14 +00:00
b00b267bcc
Fix PR2634. Create new virtual registers from spills early so that we
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can give it the same stack slot as the spilled interval if it is folded.
This prevents the fold/unfold code from pointing to the wrong register.
llvm-svn: 58255
2008-10-27 17:38:59 +00:00
4bac4d0a16
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now).
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llvm-svn: 58068
2008-10-24 02:05:00 +00:00
2dadd3bbc6
By min, I mean max.
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llvm-svn: 57766
2008-10-18 05:21:37 +00:00
ac4e70d946
When creating intervals, leave min(1, numdefs) holes after each instruction.
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llvm-svn: 57765
2008-10-18 05:18:55 +00:00
1d338fc6a4
Add an option to enable StrongPHIElimination, for ease of testing.
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llvm-svn: 57259
2008-10-07 20:22:28 +00:00
0d1e9a8e04
Switch the MachineOperand accessors back to the short names like
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isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
f4a36407c7
Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down.
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llvm-svn: 56889
2008-09-30 22:51:54 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
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llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
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"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
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llvm-svn: 56835
2008-09-30 06:36:58 +00:00
c36660d756
Next round of earlyclobber handling. Approach the
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RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
llvm-svn: 56539
2008-09-24 01:07:17 +00:00
df8f1cb995
Fetch the starting index of the block when assigning intervals. This gets live-in indices
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correct in the presence of things like EH labels.
llvm-svn: 56410
2008-09-21 20:43:24 +00:00
e519bd4183
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
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and redo as linked list walk. Logic moved into RA.
Per review feedback.
llvm-svn: 56326
2008-09-19 01:02:35 +00:00
f8610ebebc
Add a bit to mark operands of asm's that conflict
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with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
llvm-svn: 56290
2008-09-17 21:13:11 +00:00
82ab1e7280
Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
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instruction. Also, their valno's should have an unknown def. This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.
llvm-svn: 56231
2008-09-15 22:00:38 +00:00
38453eebdc
Remove isImm(), isReg(), and friends, in favor of
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isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
2008-09-13 17:58:21 +00:00
2a458775db
Allow the fast-path spilling code to attempt folding, but still leaving out remat and splitting.
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llvm-svn: 55012
2008-08-19 22:12:11 +00:00
c75ae13566
The fast-path still needs to set kill markers and spill/restore points as appropriate.
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With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.
llvm-svn: 55000
2008-08-19 20:09:52 +00:00
442dc6fed0
Add a flag to enable the fast spilling path.
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llvm-svn: 54958
2008-08-19 00:17:30 +00:00
a57c57067d
Fix a few more bugs:
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1) Assign stack slots to new temporaries.
2) Don't insert an interval into the return vector more than once.
llvm-svn: 54956
2008-08-18 23:41:04 +00:00
60f6b2cac0
Fix several bugs in the new fast-path:
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1) Remove an incorrect assertion.
2) Set the stack slot weight properly.
3) Resize the VirtRegMap when needed.
llvm-svn: 54949
2008-08-18 21:20:32 +00:00
e996a12f27
Clients of addIntervalForSpills expect the added intervals to be returned sorted by starting index.
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llvm-svn: 54939
2008-08-18 19:52:22 +00:00
75e27d2402
Simplify the fast-patch interval spilling by using MachineRegisterInfo::reg_iterator.
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llvm-svn: 54930
2008-08-18 18:38:12 +00:00
cc9314ba32
Resurrect some ancient code to add spill ranges without attempting folding, remat, or splitting. This code has been updated to current APIs
...
in so far as it compiles and, in theory, works, but does not take advantage of recent advancements. For instance, it could be improved by using
MachineRegisterInfo::use_iterator.
llvm-svn: 54924
2008-08-18 18:05:32 +00:00
706f6b7899
Expunge the last uses of std::map from LiveIntervals.
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llvm-svn: 54766
2008-08-13 22:28:50 +00:00
767b5cc7fd
Move r2iMap_ over to DenseMap from std::map.
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llvm-svn: 54765
2008-08-13 22:08:30 +00:00
51f689a652
Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated
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if the map is changed.
llvm-svn: 54763
2008-08-13 21:49:13 +00:00
d184929176
Oops, didn't mean to commit this.
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llvm-svn: 54425
2008-08-06 20:58:38 +00:00
03dddbbed5
Only remap each VNInfo once when doing renumbering.
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llvm-svn: 54420
2008-08-06 18:35:45 +00:00
7b5f535590
Value numbers whose def index is a special sentinel value should not be remapped.
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llvm-svn: 54218
2008-07-30 17:42:47 +00:00
e9a0bae238
More fixes for corner cases when remapping live range indices.
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llvm-svn: 54186
2008-07-30 00:22:56 +00:00
2532e75933
Don't decrement the BB remap when we don't need to.
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llvm-svn: 54173
2008-07-29 21:15:44 +00:00
804c95df52
Fold the useful features of alist and alist_node into ilist, and
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a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.
Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.
Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.
llvm-svn: 54146
2008-07-28 21:51:04 +00:00
24b3ce1db6
Fix a typo in a comment.
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llvm-svn: 54136
2008-07-28 18:43:51 +00:00
7a45b168ac
Revert my previous patch. In retrospect, this is completely the wrong way to fix this problem.
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llvm-svn: 54072
2008-07-25 23:06:59 +00:00
074f9db2fd
Special cases are needed in renumbering when dealing with renumbering after a PHI has been removed. The interval previously defined
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by the PHI needs to be extended to the beginning of its basic block, and the intervals that were inputs need to be trimmed to the end
of their basic blocks.
llvm-svn: 54070
2008-07-25 22:32:01 +00:00
88499a3503
Properly remap live ranges whose end indices are the end of the function.
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llvm-svn: 54061
2008-07-25 21:07:13 +00:00
c7d53fd331
Make the remapping of interval indices (particularly ending indices) more robust.
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This is tricky business, and will probably take a few more iterations to get
the last kinks out of it.
llvm-svn: 54043
2008-07-25 19:50:48 +00:00
394ec3ab5a
Disable the new aggressive remat logic introduced in 54000; it causes some
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regressions, such as PR2595. Also, there is a significant code-quality
issue in SPEC 464.h264ref and a few others.
llvm-svn: 54014
2008-07-25 15:08:37 +00:00
09b0448dbc
Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory,
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and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.
llvm-svn: 54000
2008-07-25 00:02:30 +00:00
50d393a68d
Enable the insertion of empty indices into LiveInterals, thereby making renumbering possible.
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llvm-svn: 53961
2008-07-23 21:37:49 +00:00
7c800ad977
Fix a compile-time regression introduced by my heuristic-changing patch. I forgot
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to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.
llvm-svn: 53959
2008-07-23 19:47:27 +00:00
029182f3a3
Change the heuristics used in the coalescer, register allocator, and within
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live intervals itself to use an instruction count approximation that is
not affected by inserting empty indices.
llvm-svn: 53937
2008-07-22 22:46:49 +00:00
a7a20c4946
Fix a memory leak in LiveIntervalAnalysis.
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llvm-svn: 53779
2008-07-19 00:37:25 +00:00
0ece943845
Re-introduce LeakDetector support for MachineInstrs and MachineBasicBlocks.
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Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.
llvm-svn: 53746
2008-07-17 23:49:46 +00:00
2b3c52d5c4
Typos.
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llvm-svn: 53504
2008-07-12 02:22:07 +00:00
e0a352e8e7
Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
...
8 %reg1024<def> = IMPLICIT_DEF
12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.
llvm-svn: 53503
2008-07-12 01:56:02 +00:00
e9ba28dd68
- Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
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- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.
llvm-svn: 53394
2008-07-10 07:35:43 +00:00
3b46030375
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
2008-07-07 23:14:23 +00:00
7d98a48f15
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
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- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
llvm-svn: 53097
2008-07-03 09:09:37 +00:00
b55675e1db
Remember which MachineOperand we were processing, so we don't have to scan the list to find it again later.
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This speeds up live intervals from 0.37s to 0.30s on instcombine.
llvm-svn: 52745
2008-06-25 23:39:39 +00:00
f593a65497
Undo spill weight tweak. Need to investigate the performance regressions.
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llvm-svn: 52572
2008-06-21 06:45:54 +00:00
3c4ccc830e
Revert my last patch, which was causing regression test failures.
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llvm-svn: 52485
2008-06-19 05:29:34 +00:00
55bc848640
Minor spiller tweak to unfavor reload into load/store instructions.
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llvm-svn: 52477
2008-06-19 01:16:17 +00:00
80ef880b98
Insert empty slots into the instruction numbering in live intervals, so that we can more easily
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add new instructions.
llvm-svn: 52475
2008-06-19 00:10:49 +00:00
f873ed1b10
Live-through live interval is [mbb start, mbb end+1].
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llvm-svn: 52431
2008-06-17 20:13:36 +00:00
476e91ab75
Remove special case handling of empty MBBs now that we assign indices to them.
...
llvm-svn: 52345
2008-06-16 19:32:40 +00:00
773b2d3ac3
Re-enable empty block indexing by default, since it doesn't seem to have any
...
impact on code quality or compile time.
llvm-svn: 52329
2008-06-16 16:58:24 +00:00
e546c55e59
Make indexing empty basic blocks an option for the moment.
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llvm-svn: 52306
2008-06-16 07:10:49 +00:00
d813091cde
Assign indices to empty basic blocks. This will be necessary for StrongPHIElimination in the near future.
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llvm-svn: 52300
2008-06-16 06:18:41 +00:00
6d7a144453
Refine stack slot interval weight computation.
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llvm-svn: 52040
2008-06-06 07:54:39 +00:00
35e2dfe1cf
Add a helper for constructing new live ranges that ended from an instruction to the end of its MBB.
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llvm-svn: 52012
2008-06-05 17:15:43 +00:00
12a0222a01
Add a stack slot coloring pass. Not yet enabled.
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llvm-svn: 51934
2008-06-04 09:18:41 +00:00
0908deccc2
Correctly handle removed instructions at the beginning of MBBs when renumbering.
...
llvm-svn: 51876
2008-06-02 17:36:36 +00:00
82fc4cdafb
Make the renumbering correct in the face of deleted instructions that have been removed from the LiveIntervals maps.
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llvm-svn: 51714
2008-05-29 23:01:22 +00:00
bf5b228c32
Remove <iostream>.
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llvm-svn: 51704
2008-05-29 21:29:39 +00:00
d95dcd12c9
Revert part of my last patch that I didn't intend to commit yet.
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llvm-svn: 51694
2008-05-29 18:35:21 +00:00
0178e95791
Renumbering needs to account for instruction slot offsets when performing lookups in the index maps.
...
llvm-svn: 51691
2008-05-29 18:15:49 +00:00
779b4180dc
Remap VNInfo data as well when doing renumbering.
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llvm-svn: 51658
2008-05-28 22:40:08 +00:00
4f8e1ad32a
Factor the numbering computation into a separate method, and add the slightest attempt at some renumbering logic, which is currently unused.
...
llvm-svn: 51652
2008-05-28 20:54:50 +00:00
7c0db62a5e
Revert 51440 as it breaks a bunch of PIC tests.
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llvm-svn: 51513
2008-05-23 23:00:04 +00:00
830487035e
When rewriting defs and uses after spilling, don't set the weight of a
...
live interval to infinity if the instruction being rewritten is an
original remat def instruction. We were only checking against the clone
of the remat def which doesn't actually appear in the IR at all.
llvm-svn: 51440
2008-05-22 21:16:33 +00:00
c8b028daa4
Don't spill dead def.
...
llvm-svn: 51305
2008-05-20 08:10:37 +00:00
d78c400b5b
Clean up the use of static and anonymous namespaces. This turned up
...
several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
2008-05-13 00:00:25 +00:00
6a2da37c0e
Make several variable declarations static.
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llvm-svn: 50696
2008-05-06 01:53:16 +00:00
8dc8a8d8af
Empty basic block should have an empty range.
...
llvm-svn: 49800
2008-04-16 18:01:08 +00:00
499ffa9055
Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled.
...
llvm-svn: 49542
2008-04-11 17:53:36 +00:00
c8eeb752a3
- More aggressively coalescing away copies whose source is defined by an implicit_def.
...
- Added insert_subreg coalescing support.
llvm-svn: 49448
2008-04-09 20:57:25 +00:00
20aed56504
- Treat a live range defined by an implicit_def as a zero-sized one.
...
- Eliminate an implicit_def when it's being spilled.
llvm-svn: 49166
2008-04-03 16:39:43 +00:00
985a0b51d7
Re-materialization is for uses only.
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llvm-svn: 49053
2008-04-01 21:37:32 +00:00
e4f77c69ac
It's not safe to fold a load from GV stub or constantpool into a two-address use.
...
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
73d7c3bfba
The support for remat of instructions with a register operand is hackish, to say the least. Since the register operand guaranteed to be PIC base and that it is already live at all uses, we are making sure it will not be spilled after its uses are rematerialized for both performance and correctness reasons.
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llvm-svn: 48976
2008-03-31 07:53:30 +00:00
ec7533b620
Remove isImplicitDef TargetInstrDesc flag.
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llvm-svn: 48381
2008-03-15 00:19:36 +00:00
a3891365b5
Transfer physical register spill info when load / store folding happens.
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llvm-svn: 48246
2008-03-11 21:34:46 +00:00
Evan Cheng