8523b16ff5
Instruction scheduling itinerary for Intel Atom.
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Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
9f05206659
Avoid creating an extract element to an illegal type after LegalizeTypes has run.
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llvm-svn: 149548
2012-02-01 22:15:20 +00:00
e273cb08c4
Tidy up.
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llvm-svn: 149521
2012-02-01 18:45:51 +00:00
34cca175ab
Shortened code in shuffle masks
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llvm-svn: 149493
2012-02-01 10:33:05 +00:00
0e48c70ba7
Optimization for "truncate" operation on AVX.
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Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
llvm-svn: 149485
2012-02-01 07:56:44 +00:00
9cdb8bdf04
Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
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llvm-svn: 149478
2012-02-01 06:51:58 +00:00
b85e40f738
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
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llvm-svn: 149367
2012-01-31 06:52:44 +00:00
396c590818
Fix refacto.
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llvm-svn: 149269
2012-01-30 20:01:35 +00:00
e577cfe172
Eliminate narrowing conversion in initializer list, to make C++11 happy
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llvm-svn: 149254
2012-01-30 16:57:18 +00:00
20af25f47b
X86: Simplify shuffle mask generation code.
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llvm-svn: 149248
2012-01-30 15:16:21 +00:00
516cba3380
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
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llvm-svn: 149232
2012-01-30 07:50:31 +00:00
ca29bcfc10
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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llvm-svn: 149216
2012-01-30 01:10:15 +00:00
b91760eff8
Remove some more patterns by custom lowering intrinsics to target specific nodes.
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llvm-svn: 149052
2012-01-26 07:18:03 +00:00
33633a90a0
fix a bug I introduced in r148929, this is not a splat!
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Thanks to Eli for noticing.
llvm-svn: 148947
2012-01-25 09:56:22 +00:00
7834900950
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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llvm-svn: 148933
2012-01-25 06:43:11 +00:00
47a86bdbe2
use ConstantVector::getSplat in a few places.
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llvm-svn: 148929
2012-01-25 06:02:56 +00:00
ce4f9c5668
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
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llvm-svn: 148927
2012-01-25 05:37:32 +00:00
0b0c5d8c4c
ZERO_EXTEND operation is optimized for AVX.
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v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
llvm-svn: 148803
2012-01-24 13:54:13 +00:00
edd1d0acfc
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
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llvm-svn: 148687
2012-01-23 08:18:28 +00:00
6b90c5d03e
Update more places to use target specific nodes for vector shifts instead of intrinsics.
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llvm-svn: 148685
2012-01-23 06:46:22 +00:00
5e80db4e4f
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
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llvm-svn: 148684
2012-01-23 06:16:53 +00:00
0b7ad76bd0
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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llvm-svn: 148670
2012-01-22 23:36:02 +00:00
bd4884371b
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
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llvm-svn: 148667
2012-01-22 22:42:16 +00:00
094626414d
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
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llvm-svn: 148664
2012-01-22 19:15:14 +00:00
a4ed5246d8
Make code a little less verbose.
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llvm-svn: 148651
2012-01-22 03:07:48 +00:00
cb3433cd58
Remove unused X86 ISD node type defines.
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llvm-svn: 148644
2012-01-22 01:15:56 +00:00
39bc1e4d25
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
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llvm-svn: 148632
2012-01-21 08:49:33 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
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llvm-svn: 148578
2012-01-20 21:51:11 +00:00
a409479023
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
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llvm-svn: 148537
2012-01-20 09:29:03 +00:00
3469212c82
Add support for selecting 256-bit PALIGNR.
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llvm-svn: 148532
2012-01-20 05:53:00 +00:00
32c7c25dcb
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
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llvm-svn: 148513
2012-01-20 00:05:46 +00:00
80576e8d1f
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
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llvm-svn: 148466
2012-01-19 08:19:12 +00:00
ecc0084f72
Add a TargetOption for disabling tail calls.
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llvm-svn: 148442
2012-01-19 00:34:10 +00:00
ff482f733b
Add experimental -x86-use-regmask command line option.
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It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
llvm-svn: 148438
2012-01-18 23:52:22 +00:00
86c3807b99
Fix warning.
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llvm-svn: 148301
2012-01-17 09:31:09 +00:00
86e5390dbf
Fix 11769.
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In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
llvm-svn: 148298
2012-01-17 09:13:19 +00:00
9cafcd8baa
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
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llvm-svn: 148295
2012-01-17 08:23:44 +00:00
37b10ef250
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
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llvm-svn: 148285
2012-01-17 04:44:50 +00:00
57935243bd
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
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We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.
Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.
llvm-svn: 148225
2012-01-15 19:27:55 +00:00
339ced4e34
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
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llvm-svn: 148218
2012-01-15 13:16:05 +00:00
b1c2ebf6ee
use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
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llvm-svn: 148109
2012-01-13 08:32:21 +00:00
cb7e13d7c0
Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
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llvm-svn: 148108
2012-01-13 08:12:35 +00:00
2aa07f832e
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
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llvm-svn: 148096
2012-01-13 05:04:25 +00:00
060f6ccdb8
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
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lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
llvm-svn: 148044
2012-01-12 20:33:10 +00:00
0a0a829bea
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
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The attached testcase was stuck in an endless loop.
llvm-svn: 148027
2012-01-12 15:31:55 +00:00
6635ae1c17
Explicitly set the scale to 1 on some segstack prologue instrs.
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Patch by Brian Anderson.
llvm-svn: 147952
2012-01-11 18:14:03 +00:00
baae7e4577
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead.
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llvm-svn: 147948
2012-01-11 14:07:51 +00:00
995c63329a
Fixed order of operands in comment to match code.
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llvm-svn: 147890
2012-01-10 22:53:20 +00:00
d5ab02600e
For i386, don't use the generic code.
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As the comment around 7746 says, it's better to use the x87 extended precision
here than SSE. And the generic code doesn't know how to do that. It also regains
the speed lost for the uint64_to_float.c testcase.
<rdar://problem/10669858>
llvm-svn: 147869
2012-01-10 19:41:30 +00:00
430f3f1bd6
Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside.
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llvm-svn: 147844
2012-01-10 08:23:59 +00:00
Andrew Trick