Commit Graph

341884 Commits

Author SHA1 Message Date
Simon Pilgrim c96001035d [X86] isNegatibleForFree - allow pre-legalized FMA negation
As long as the FMA operation is legal (which we can proxy for the FMA3/FMA4 variants as well), we don't have to wait for the LegalOperations stage.
2020-02-07 17:04:17 +00:00
Amara Emerson 28d22c2c9c [GlobalISel][IRTranslator] Add special case support for ~memory inline asm clobber.
This is a one off special case, since actually implementing full inline asm
support will be much more involved. This lets us compile a lot more code as a
common simple case.

Differential Revision: https://reviews.llvm.org/D74201
2020-02-07 08:55:23 -08:00
Michał Górny 1ff411295f [lldb] Improve debugging 32-bit programs on NetBSD/amd64
Implement detection of ELF binary format, and support for i386 register
context on amd64 when a 32-bit executable is being debugged.  This is
roughly based on the code from Linux.

Differential Revision: https://reviews.llvm.org/D73974
2020-02-07 17:48:33 +01:00
Med Ismail Bennani 96054a1857 [lldb/test] Prevent TestFrameRecognizer.py to fail because of internal recognizers (NFC)
By clearing the recognizers before starting the test, we ensure that the
recognizers that get initialized when lldb starts won't alter the
expected results of this test (i.e. recognizer index).

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-02-07 17:35:29 +01:00
Med Ismail Bennani 047c4b0369 [lldb/Target] Fix `frame recognizer list` crash when registered with nullptr
One way to register a recognizer is to use RegularExpressionSP for the
module and symbol.

In order to match a symbol regardless of the module, the recognizer can
be registered with a nullptr for the module. However, this cause the
frame recognizer list command to crash because it calls
RegularExpression::GetText without checking if the shared pointer is valid.

This patch adds checks for the symbol and module RegularExpressionSP.

Differential Revision: https://reviews.llvm.org/D74212

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-02-07 17:35:29 +01:00
Nuno Lopes 380fe91fc6 [docs] update mathjax path in doxygen 2020-02-07 16:26:35 +00:00
Jinsong Ji 01edae1271 [AsmPrinter] Print FP constant in hexadecimal form instead
Printing floating point number in decimal is inconvenient for humans.
Verbose asm output will print out floating point values in comments, it
helps.

But in lots of cases, users still need additional work to covert the
decimal back to hex or binary to check the bit patterns,
especially when there are small precision difference.

Hexadecimal form is one of the supported form in LLVM IR, and easier for
debugging.

This patch try to print all FP constant in hex form instead.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D73566
2020-02-07 16:00:55 +00:00
Miloš Stojanović 205292740d [llvm-exegesis] Improve error reporting in BenchmarkRunner.cpp
Followup to D74085.
Replace the use of `report_fatal_error()` with returning the error to
`llvm-exegesis.cpp` and handling it there.
To facilitate this, a new `Error` type has been added which is only used
to log errors to the yaml output.

Differential Revision: https://reviews.llvm.org/D74215
2020-02-07 16:29:52 +01:00
Matt Arsenault 2f885cbe90 AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
We were executing this in a waterfall loop as a placeholder, but this
should really be converted to a MUBUF load. Also execute in a
waterfall loop if the resource isn't an SGPR. This is a case where the
DAG handling was wrong because doing the right thing was too hard.

Currently, this will mishandle 96-bit loads. There's currently no way
to track the original memory size with an MMO, so these loads will be
widened andd the resulting memory size will be 128-bits.
2020-02-07 07:19:01 -08:00
Simon Tatham 5c6b1a6dfd [TableGen] Fix spurious type error in bit assignment.
Summary:
The following example gives the error message "expected value of type
'bits<32>', got 'bit'" on the assignment.

    class Instruction { bits<32> encoding; }
    def foo: Instruction { let encoding{10} = !eq(0, 1); }

But there's nothing wrong with this code: 'bit' is a perfectly good
type for the RHS of an assignment to a //single bit// of an
instruction encoding.

The problem is that `ParseBodyItem` is accidentally type-checking the
RHS against the full type of the `encoding` field, without adjusting
it in the case where we're only assigning to a subset of the bits. The
fix is trivial.

Reviewers: nhaehnle, hfinkel

Reviewed By: hfinkel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74220
2020-02-07 15:11:42 +00:00
Matt Arsenault 3b198518ad GlobalISel: Fix narrowing of G_CTPOP
The result type is separate from the source type. Tests will be
included in a future AMDGPU patch which uses this from
RegBankSelect/applyMappingImpl.
2020-02-07 06:58:00 -08:00
Matt Arsenault 8de2dad9e0 GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
The type passed to lower was invalid, so I'm not sure how this was
even working before. The source and destination type also do not have
to match, so make sure to use the right ones.
2020-02-07 06:54:12 -08:00
Alexandre Ganea 75f09b5442 Re-land "[Clang][Driver] Remove -M group options ..." and "[Clang] Avoid crashing when generating crash diagnostics when '#pragma clang __debug ..."
This re-lands commits f41ec709d9 (https://reviews.llvm.org/D74076)
and commit 5fedc2b410 (https://reviews.llvm.org/D74070)

The previous build break was caused by '#pragma clang __debug llvm_unreachable' used in a non-assert build. Move it to a separate test in crash-report-with-asserts.c.
2020-02-07 09:51:09 -05:00
Alexey Bataev ea9166b5a8 [OPENMP50]Add parsing/sema for acq_rel clause.
Added basic support (representation + parsing/sema/(de)serialization)
for acq_rel clause in flush/atomic directives.
2020-02-07 09:21:10 -05:00
Sam Parker 2db5547c01 [NFC][ARM] Update test 2020-02-07 14:20:19 +00:00
OuHangKresnik 7edf27f7a7 [mlir] Add NoSideEffect to Affine min max
Add NoSideEffect to Affine min and max operations.

Differential Revision: https://reviews.llvm.org/D74203
2020-02-07 15:19:48 +01:00
Nico Weber c29003813a Revert "[LLD][ELF][ARM] Do not substitute BL/BLX for non STT_FUNC symbols."
There are still problems after the fix in
"[ELF][ARM] Fix regression of BL->BLX substitution after D73542"
so let's revert to get trunk back to green while we investigate.
See https://reviews.llvm.org/D73542

This reverts commit 5461fa2b1f.
This reverts commit 0b4a047bfb.
2020-02-07 08:55:52 -05:00
Sam Parker 441cafb881 [NFC][ARM] Modified test with update script 2020-02-07 13:43:34 +00:00
LLVM GN Syncbot 1ea2723eb5 [gn build] Port 446268a223 2020-02-07 13:35:48 +00:00
Miloš Stojanović 4bd40f71a7 Recommit: "[llvm-exegesis] Improve error reporting in Target.cpp"
Summary: Commit 141915963b was reverted in
abe01e17f6 because it broke builds testing
without libpfm. A preparatory commit <commit_sha1> was added to enable
this recommit.

Original commit message:

Followup to D74085.
Replace the use of `report_fatal_error()` with returning the error to
`llvm-exegesis.cpp` and handling it there.

Differential Revision: https://reviews.llvm.org/D74113
2020-02-07 14:34:58 +01:00
Miloš Stojanović 830af528a5 Recommit: "[llvm-exegesis] Improve error reporting"
Summary: Commit b3576f60eb was reverted in
abe01e17f6 because it broke builds testing
without libpfm. A preparatory commit <commit_sha1> was added to enable
this recommit.

Original commit message:

Fix inconsistencies in error reporting created by mixing
`report_fatal_error()` and `ExitOnErr()`, and add additional information
to the error message to make it more user friendly. Minimize the use
`report_fatal_error()` because it's meant for use in very rare cases and
it results in low information density of the error messages.

Summary of the new design:

 * For command line argument errors output `llvm-exegesis: <error_message>`,
   which is consistent with the error output format emitted by the backend
   which checks correctness of the command line arguments.
 * For other errors the format `llvm-exegesis error: <error_message>` is used.
 ** If the error occurred during file access `<error_message>` will have
    of two parts: `'<file_name>': <rest_of_the_error_message>`

Differential Revision: https://reviews.llvm.org/D74085
2020-02-07 14:34:58 +01:00
Miloš Stojanović 446268a223 [llvm-exegesis] Add a custom error for clustering
All errors of type `Failure` are `StringError`s. In order for exit code
mapping to detect that specifically a clustering error has occurred it
needs to have a different type.

This patch also prepares D74085 where termination `report_fatal_error()`
will be replaced with emitting `StringError`s.

Differential Revision: https://reviews.llvm.org/D74124
2020-02-07 14:34:57 +01:00
Dmitry Preobrazhensky 2de2275cbd [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- updated description of gfx906 and gfx908;
- added description of gfx1011 and gfx1012 subtargets.
2020-02-07 16:23:46 +03:00
Christian Sigg 5a21d2bbb9 Rename prettyprinters test to llvm-support.
Summary: Make room for mlir-support pretty printers that I would like to add next.

Reviewers: dblaikie

Reviewed By: dblaikie

Subscribers: merge_guards_bot, mgorny, rriddle, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73726
2020-02-07 14:05:26 +01:00
Raphael Isemann 0082f1e0cc [lldb] Improve error message when running static initializers in an expression fails 2020-02-07 13:46:28 +01:00
Momchil Velikov a2531081b3 [AArch64] Predictably disassemble system registers with the same encoding
The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers,
defined by separate extension specifications (ETM and ETE,
respectively), yet they use the same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would
essentially return a random one, depending on the number, relative
position in the TableGen file, whether the TableGen records for system
registers are named or not, and, if they are named, depending on
record (not register!) name as well.

This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.

Differential Revision: https://reviews.llvm.org/D74074
2020-02-07 12:19:57 +00:00
Anastasia Stulova 6064f426a1 [OpenCL] Restrict addr space conversions in nested pointers
Address space conversion changes pointer representation.
This commit disallows such conversions when they are not
legal i.e. for the nested pointers even with compatible
address spaces. Because the address space conversion in
the nested levels can't be generated to modify the pointers
correctly. The behavior implemented is as follows:

- Any implicit conversions of nested pointers with different
  address spaces is rejected.
- Any conversion of address spaces in nested pointers in safe
  casts (e.g. const_cast or static_cast) is rejected.
- Conversion in low level C-style or reinterpret_cast is accepted
  but with a warning (this aligns with OpenCL C behavior).

Fixes PR39674

Differential Revision: https://reviews.llvm.org/D73360
2020-02-07 12:04:35 +00:00
Hans Wennborg 64bc627b88 clang-cl: Parse new MSVC flags /Qspectre-load and /Qspectre-load-cf
See 2fdf0ba0bf
2020-02-07 13:00:52 +01:00
Djordje Todorovic d173cb1db7 [llvm-dwarfdump][Stats] Add the license header
Add the License header into the Statistics.cpp.

Differential Revision: https://reviews.llvm.org/D74207
2020-02-07 12:37:32 +01:00
Florian Hahn 14ef87bda6 [ValueTracking] usub(a, b) cannot overflow if a >= b.
If we know that a >= b (unsigned), usub.with.overflow(a, b) cannot
overflow. Similarly, if b > a, the same expression overflows.

Reviewers: nikic, RKSimon, lebedev.ri, spatel

Reviewed By: nikic, Gerolf

Differential Revision: https://reviews.llvm.org/D74066
2020-02-07 10:41:18 +00:00
Hans Wennborg 74734e809a Fix docs and comments for max_tokens_total pragma 2020-02-07 11:37:14 +01:00
serge-sans-paille f6d98429fc Revert "Support -fstack-clash-protection for x86"
This reverts commit 39f50da2a3.

The -fstack-clash-protection is being passed to the linker too, which
is not intended.

Reverting and fixing that in a later commit.
2020-02-07 11:36:53 +01:00
Balázs Kéri c4f0f8ec41 [analyzer] Small StreamChecker refactoring (NFC).
Reviewers: Szelethus

Reviewed By: Szelethus

Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, donat.nagy, Charusso, dkrupp, Szelethus, gamesh411, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73350
2020-02-07 11:35:46 +01:00
Guillaume Chatelet f85d3408e6 [NFC] Introduce an API for MemOp
Summary: This patch introduces an API for MemOp in order to simplify and tighten the client code.

Reviewers: courbet

Subscribers: arsenm, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jsji, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73964
2020-02-07 11:32:27 +01:00
Florian Hahn 89ca4b9ef2 [InstCombine] Precommit usub.with.overflow test for D74066. 2020-02-07 10:30:28 +00:00
Florian Hahn 8d5e76ac30 [ValueTracking] Update implied reasoning to accept expanded cmp (NFC).
This patch adds versions of isImpliedCondition and
isImpliedByDomCondition that take a predicate, LHS and RHS operands as
instead of a Value representing the condition.

This allows using those functions to check conditions without having a
concrete ICmp instruction.

Reviewers: nikic, RKSimon, lebedev.ri, spatel

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D74065
2020-02-07 10:27:29 +00:00
Raphael Isemann 68cc9f80a6 [lldb] Remove all 'clean' targets from test Makefiles
Summary:
To my knowledge we don't actually use or need these rules. And if we need them then
there is probably a better way to implement this than having all these random regexes.

Reviewers: labath, JDevlieghere

Reviewed By: labath, JDevlieghere

Subscribers: jingham, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74126
2020-02-07 11:24:52 +01:00
Diogo Sampaio 9d869180c4 [ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields
Summary:
Following the AAPCS, every store to a volatile bit-field requires to generate one load of that field, even if all the bits are going to be replaced.
This patch allows the user to opt-in in following such rule, whenever the a.

AAPCS Release 2019Q1.1 (https://static.docs.arm.com/ihi0042/g/aapcs32.pdf)
section 8.1 Data Types, page 35, paragraph: Volatile bit-fields – preserving number and width of container accesses

```
When a volatile bit-field is written, and its container does not overlap with any non-bit-field member, its
container must be read exactly once and written exactly once using the access width appropriate to the
type of the container. The two accesses are not atomic.

```

Reviewers: lebedev.ri, ostannard, jfb, eli.friedman

Reviewed By: jfb

Subscribers: rsmith, rjmccall, dexonsmith, kristof.beyls, jfb, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D67399
2020-02-07 10:11:54 +00:00
Pierre van Houtryve e8c3a6c260 [ARM][ASMParser] Refuse equal RdHi/RdLo for s/umlal, smlsl, s/umull, umaal
Differential Revision: https://reviews.llvm.org/D74120
2020-02-07 10:05:20 +00:00
serge_sans_paille 39f50da2a3 Support -fstack-clash-protection for x86
Implement protection against the stack clash attack [0] through inline stack
probing.

Probe stack allocation every PAGE_SIZE during frame lowering or dynamic
allocation to make sure the page guard, if any, is touched when touching the
stack, in a similar manner to GCC[1].

This extends the existing `probe-stack' mechanism with a special value `inline-asm'.
Technically the former uses function call before stack allocation while this
patch provides inlined stack probes and chunk allocation.

Only implemented for x86.

[0] https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt
[1] https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00556.html

Differential Revision: https://reviews.llvm.org/D68720
2020-02-07 10:56:15 +01:00
Pierre van Houtryve 56d81d4580 [Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 & ICC_SEIEN_EL1 from AArch64 backend
Differential Revision: https://reviews.llvm.org/D74118
2020-02-07 09:44:41 +00:00
Hans Wennborg 81c9df1023 Fix the MC/WebAssembly/debug-info.ll test after 84e5760 2020-02-07 09:54:05 +01:00
Konrad Kleine b89131cdda [lldb] removed no longer needed CMakeDependentOption
Summary:
In D66791 I've introduced this [[ https://cmake.org/cmake/help/latest/module/CMakeDependentOption.html | `CMakeDependentOption` ]] but in
D71306 @JDevlieghere has changed the way optional dependencies
are handled in LLDB. Today there's no occurence of
`cmake_dependent_option` inside the lldb source tree.

That's why this include can be removed.

Reviewers: JDevlieghere, labath

Reviewed By: labath

Subscribers: labath, mgorny, lldb-commits, JDevlieghere

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74160
2020-02-07 09:23:35 +01:00
Sourabh Singh Tomar 84e5760a16 [DebugInfo]: Reorderd the emission of debug_str section.
Summary:
This patch reorders the emission of debug_str section, so that
string can come after macros.
This is necessary for macro forms like DW_MACRO_define_strp,
which emits macro as a string in debug_str section.
2020-02-07 11:15:55 +05:30
Craig Topper ae4e49868a [X86] Turn vXi1 any_extends into sign_extends in PreprocessISelDAG and remove some isel patterns.
Similar to what we do for other vector any_extends, but instead
of zero_extend we need to use sign_extend.
2020-02-06 21:32:53 -08:00
Craig Topper 3f62028f2f [X86] Use SelectionDAG::getAllOnesConstant to simplify some code. NFC 2020-02-06 21:32:53 -08:00
Jason Molenda f60de4cdf7 Except, get the TARGET_OS_OSX check correct. 2020-02-06 20:28:40 -08:00
Jason Molenda e2fa760cdd Fix my use of the TARGET_OS_OSX TargetConditional. 2020-02-06 20:28:28 -08:00
Justin Lebar 6d007343de Clarify how llvm-mca detects att vs intel syntax.
Reviewers: andreadb

Subscribers: tschuett, gbedwell, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72385
2020-02-06 19:35:09 -08:00
Matt Arsenault 6a570dc548 AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts
These wouldn't legalize between 16-bits and 32-bits on targets with
16-bit instructions.
2020-02-06 21:43:54 -05:00